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Andrew Laffely
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Journal Articles
- 2004
- [j2]Jian Liang, Andrew Laffely, Sriram Srinivasan, Russell Tessier:
An architecture and compiler for scalable on-chip communication. IEEE Trans. Very Large Scale Integr. Syst. 12(7): 711-726 (2004) - [j1]Prashant Jain, Andrew Laffely, Wayne P. Burleson, Russell Tessier, Dennis Goeckel:
Dynamically Parameterized Algorithms and Architectures to Exploit Signal Variations. J. VLSI Signal Process. 36(1): 27-40 (2004)
Conference and Workshop Papers
- 2004
- [c4]Vishak Venkatraman, Andrew Laffely, Jinwook Jang, Hempraveen Kukkamalla, Zhi Zhu, Wayne P. Burleson:
NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods. SLIP 2004: 69-75 - 2003
- [c3]Andrew Laffely, Jian Liang, Russell Tessier, Wayne P. Burleson:
Adaptive system on a chip (ASOC): a backbone for power-aware signal processing cores. ICIP (3) 2003: 105-108 - [c2]Lilian Bossuet, Wayne P. Burleson, Guy Gogniat
, Vikas Anand, Andrew Laffely, Jean Luc Philippe:
Targeting Tiled Architectures in Design Exploration. IPDPS 2003: 172 - [c1]Andrew Laffely, Wayne P. Burleson:
Using System On-A-Chip As A Vehicle For VLSI Design Education. MSE 2003: 148-149
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