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Chin Hau Hoo

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2010 – 2019

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2018
[c7]
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  dblp key:
  - conf/fpga/Hoo018
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Chin Hau Hoo, Akash Kumar:
ParaDRo: A Parallel Deterministic Router Based on Spatial Partitioning and Scheduling. FPGA 2018: 67-76
2017
[c6]
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Chin Hau Hoo, Akash Kumar:
ParaDiMe: A Distributed Memory FPGA Router Based on Speculative Parallelism and Path Encoding. FCCM 2017: 172-179
2016
[c5]
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  - conf/fpl/HooH016
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Chin Hau Hoo, Yajun Ha, Akash Kumar:
ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioning. FPL 2016: 1-11
2015
[c4]
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  - conf/fpl/HooKH15
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Chin Hau Hoo, Akash Kumar, Yajun Ha:
ParaLaR: A parallel FPGA router based on Lagrangian relaxation. FPL 2015: 1-6
2013
[c3]
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Chin Hau Hoo, Yajun Ha, Akash Kumar:
A directional coarse-grained power gated FPGA switch box and power gating aware routing algorithm. FPL 2013: 1-4
[c2]
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  - conf/islped/ZhaoHHA13
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Wenfeng Zhao, Yajun Ha, Chin Hau Hoo, Anastacia B. Alvarez:
Robustness-driven energy-efficient ultra-low voltage standard cell design with intra-cell mixed-Vt methodology. ISLPED 2013: 323-328
2012
[c1]
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  - conf/fpl/HooK12
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Chin Hau Hoo, Akash Kumar:
An area-efficient partially reconfigurable crossbar switch with low reconfiguration delay. FPL 2012: 400-406

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