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John G. Maneatis

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Journal Articles

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2003
[j3]
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John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey, Manjusha Shankaradas:
Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL. IEEE J. Solid State Circuits 38(11): 1795-1803 (2003)
1996
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John G. Maneatis:
Low-jitter process-independent DLL and PLL based on self-biased techniques. IEEE J. Solid State Circuits 31(11): 1723-1732 (1996)
1993
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John G. Maneatis, Mark A. Horowitz:
Precise delay generation using coupled oscillators. IEEE J. Solid State Circuits 28(12): 1273-1282 (1993)

Conference and Workshop Papers

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2008
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Henry Chang, William Walker, John G. Maneatis, John F. Croix:
Mixed-signal simulation challenges and solutions. ICCAD 2008: 8
2003
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John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey, Manjusha Shankaradas:
Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL. DAC 2003: 688-690

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