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ORCIDRoman P. Bazylevych
Person information
- affiliation: Lviv Polytechnic National University, Ukraine
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Journal Articles
- 2000
[j1]Roman P. Bazylevych, R. A. Melnyk, O. G. Rybak:
Circuit Partitioning for FPGAs by the Optimal Circuit Reduction Method. VLSI Design 11(3): 237-248 (2000)
Conference and Workshop Papers
- 2023
- [c20]Roman Kutelmakh, Roman P. Bazylevych, Bhanu Prasad:
Solving Large Scale Uniform Traveling Salesman Problem by Using Partial Solution Expansion Method. CSIT 2023: 1-4 - 2022
- [c19]Roman P. Bazylevych, Andrii Franko:
Input decomposition by clusterization for symbolic execution. CSIT 2022: 466-469 - 2021
- [c18]Roman P. Bazylevych, Pawel Czarnul
, Andrii Franko:
Decomposition of the unit test generation task for parallel computations. CSIT (1) 2021: 1-4 - [c17]Roman P. Bazylevych, Lubov Bazylevych:
A set of nets planarization with two chains of contacts. CSIT (1) 2021: 202-205 - 2020
- [c16]Roman P. Bazylevych, Mariusz Wrzesien, Lubov Bazylevych:
A Set of Nets Planarization for Electronic Devices' Physical Design Automation. CSIT (1) 2020: 192-195 - [c15]Roman P. Bazylevych, Pawel Czarnul, Andrii Franko:
Unit Test Generation in a Cluster Using Parallel Computations and Control Flow Graph Analysis. CSIT (1) 2020: 407-410 - 2019
- [c14]Roman P. Bazylevych, Mariusz Wrzesien, Lubov Bazylevych:
Power System Islanding by the Hierarchical Clustering. CSIT (1) 2019: 145-148 - [c13]Roman P. Bazylevych, Andrii Franko:
Parallelization of Unit Tests Generation by Control Flow Graph analysis. CSIT (2) 2019: 161-164 - 2016
- [c12]Roman P. Bazylevych, Marek Palasinski, Lubov Bazylevych:
Topologically-Geometric Routing. SLIP 2016: 5:1-5:6 - 2015
- [c11]Roman P. Bazylevych, Roman Burtnyk:
Algorithms for software clustering and modularization. CSIT 2015: 30-33 - 2014
- [c10]Roman P. Bazylevych, Sergii Byelyayev, Lubov Bazylevych, Alexandr Nikolaevich Kolesenkov, Boris Kostrov, Ekaterina Ruchkina, Vladimir Ruchkin:
The analysis and optimization algorithms of the electronic circuits design. MECO 2014: 189-192 - 2013
- [c9]Roman P. Bazylevych, Lubov Bazylevych:
The methodology and algorithms for solving the very large-scale physical design automation problems: Partitioning, packaging, placement and routing. MECO 2013: 1-2 - [c8]Roman P. Bazylevych, Marek Palasinski, Lubov Bazylevych, Dmytro Yanush:
Partitioning optimization by iterative reassignment of the hierarchically built clusters with border elements. MECO 2013: 219-222 - [c7]Roman P. Bazylevych, Lubov Bazylevych:
Tutorial: Macro-modeling for solving SOC physical design automation problems. SoCC 2013: 314 - 2011
- [c6]Roman P. Bazylevych, Rémy Dupas, Bhanu Prasad, Bohdan Kuz, Roman Kutelmakh, Lubov Bazylevych:
A Parallel Approach for Solving a Large-Scale Traveling Salesman Problem. IICAI 2011: 566-579 - 2009
- [c5]Roman P. Bazylevych, Bhanu Prasad, Roman Kutelmakh, Rémy Dupas, Lubov Bazylevych:
A Decomposition Algorithm for Uniform Traveling Salesman Problem. IICAI 2009: 47-56 - 2008
- [c4]Roman P. Bazylevych, Bhanu Prasad, Roman Kutelmakh, Lubov Bazylevych:
Decomposition and Scanning Optimization Algorithms for TSP. TMFCS 2008: 110-116 - 2007
- [c3]Roman P. Bazylevych, Ihor Podolskyy, Lubov Bazylevych:
Partitioning Optimization by Recursive Moves of Hierarchically Built Clusters. DDECS 2007: 235-238 - [c2]Roman P. Bazylevych, Roman Kutelmakh, Rémy Dupas, Lubov Bazylevych:
Decomposition Algorithms for Large-scale Clustered TSP. IICAI 2007: 255-267 - 2000
- [c1]Roman P. Bazylevych:
Hierarchial clasterization, decomposition and multilevel macromodeling - the effective and efficient tools to solve the sigh and very high size combinatorial circuit type problems (abstract only). CCU 2000: 15-30
Editorship
- 2000
- [e1]Roman P. Bazylevych, Anatoliy O. Melnyk:
Proceedings of the Symposium on Contemporary Computing in Ukraine, CCU 2000, Lviv, Ukraine, February 21-25, 2000. ACM 2000, ISBN 978-1-58113-310-3 [contents]
Coauthor Index
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