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ORCIDAtsushi Takahashi 0001
Person information
- affiliation: Tokyo Institute of Technology
Other persons with the same name
- Atsushi Takahashi 0002 — Osaka Prefecture University
- Atsushi Takahashi 0003 — University of Tokyo
- Atsushi Takahashi 0004 — Hokko Chemical Industry
- Atsushi Takahashi 0005 — Chiba University
- Atsushi Takahashi 0006 — Tottori University, Faculty of Engineering, Japan
- Atsushi Takahashi 0007 — Sony Corporation
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Journal Articles
- 2023
[j42]Atsushi Takahashi
:
Report on the 28th Asia and South Pacific Design Automation Conference. IEEE Des. Test 40(3): 62-63 (2023)- [j41]Atsushi Takahashi:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 16: 1 (2023) - 2022
- [j40]Atsushi Takahashi:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 15: 1 (2022) - 2021
- [j39]Atsushi Takahashi:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 14: 1 (2021) - 2020
- [j38]Shimpei Sato, Kano Akagi, Atsushi Takahashi:
A Fast Length Matching Routing Pattern Generation Method for Set-Pair Routing Problem Using Selective Pin-Pair Connections. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 103-A(9): 1037-1044 (2020) - [j37]Atsushi Takahashi:
Message from the Editor-in-Chief. IPSJ Trans. Syst. LSI Des. Methodol. 13: 1 (2020) - 2019
- [j36]Shimpei Sato, Eijiro Sassa, Yuta Ukon, Atsushi Takahashi:
A Low Area Overhead Design Method for High-Performance General-Synchronous Circuits with Speculative Execution. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(12): 1760-1769 (2019) - 2017
- [j35]Takeshi Ihara, Toshiyuki Hongo, Atsushi Takahashi, Chikaaki Kodama:
A Routing Method Using Directed Grid-Graph for Self-Aligned Quadruple Patterning. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1473-1480 (2017) - [j34]Ahmed Awad, Atsushi Takahashi, Satoshi Tanaka, Chikaaki Kodama:
Intensity Difference Map (IDM) Accuracy Analysis for OPC Efficiency Verification and Further Enhancement. IPSJ Trans. Syst. LSI Des. Methodol. 10: 28-38 (2017) - [j33]Ahmed Awad, Atsushi Takahashi, Satoshi Tanaka, Chikaaki Kodama:
A Fast Process-Variation-Aware Mask Optimization Algorithm With a Novel Intensity Modeling. IEEE Trans. Very Large Scale Integr. Syst. 25(3): 998-1011 (2017) - 2016
- [j32]Ahmed Awad, Atsushi Takahashi, Chikaaki Kodama:
A Fast Mask Manufacturability and Process Variation Aware OPC Algorithm with Exploiting a Novel Intensity Estimation Model. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 99-A(12): 2363-2374 (2016) - 2015
- [j31]Yuta Nakatani, Atsushi Takahashi:
A Length Matching Routing Algorithm for Set-Pair Routing Problem. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2565-2571 (2015) - [j30]Chikaaki Kodama, Hirotaka Ichikawa, Koichi Nakayama, Fumiharu Nakajima, Shigeki Nojima, Toshiya Kotani, Takeshi Ihara, Atsushi Takahashi:
Self-Aligned Double and Quadruple Patterning Aware Grid Routing Methods. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(5): 753-765 (2015) - 2014
- [j29]Yiqiang Sheng, Atsushi Takahashi:
A Novel High-Performance Heuristic Algorithm with Application to Physical Design Optimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2418-2426 (2014) - [j28]Yukihide Kohira, Atsushi Takahashi:
2-SAT Based Linear Time Optimum Two-Domain Clock Skew Scheduling in General-Synchronous Framework. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(12): 2459-2466 (2014) - 2013
- [j27]Yiqiang Sheng, Atsushi Takahashi:
A New Variation of Adaptive Simulated Annealing for 2D/3D Packing Optimization. IPSJ Trans. Syst. LSI Des. Methodol. 6: 94-100 (2013) - 2011
- [j26]Atsushi Takahashi:
Foreword. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2481 (2011) - [j25]Kyosuke Shinoda, Yukihide Kohira, Atsushi Takahashi:
Single-Layer Trunk Routing Using Minimal 45-Degree Lines. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2510-2518 (2011) - 2010
- [j24]Yukihide Kohira, Atsushi Takahashi:
CAFE Router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2380-2388 (2010) - 2009
- [j23]Yukihide Kohira, Shuhei Tani, Atsushi Takahashi:
Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(4): 1106-1114 (2009) - [j22]Yoichi Tomioka, Atsushi Takahashi:
Routability Driven Via Assignment Method for 2-Layer Ball Grid Array Packages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(6): 1433-1441 (2009) - [j21]Yukihide Kohira, Suguru Suehiro, Atsushi Takahashi:
A Fast Longer Path Algorithm for Routing Grid with Obstacles Using Biconnectivity Based Length Upper Bound. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 2971-2978 (2009) - [j20]Yoichi Tomioka, Yoshiaki Kurata, Yukihide Kohira, Atsushi Takahashi:
MILP-Based Efficient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(12): 2998-3006 (2009) - 2008
- [j19]Yukihide Kohira, Atsushi Takahashi:
A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(10): 3030-3037 (2008) - [j18]Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi:
Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3539-3547 (2008) - [j17]Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi:
A Fast Clock Scheduling for Peak Power Reduction in LSI. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3803-3811 (2008) - 2007
- [j16]Yukihide Kohira, Atsushi Takahashi:
Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(4): 800-807 (2007) - [j15]Bakhtiar Affendi Rosdi, Atsushi Takahashi:
Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 90-A(12): 2736-2742 (2007) - 2006
- [j14]Atsushi Takahashi:
Practical Fast Clock-Schedule Design Algorithms. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(4): 1005-1011 (2006) - [j13]Bakhtiar Affendi Rosdi, Atsushi Takahashi:
Multi-Clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3435-3442 (2006) - [j12]Yoichi Tomioka, Atsushi Takahashi:
Routing of Monotonic Parallel and Orthogonal Netlists for Single-Layer Ball Grid Array Packages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3551-3559 (2006) - [j11]Yukiko Kubo, Atsushi Takahashi:
Global Routing by Iterative Improvements for Two-Layer Ball Grid Array Packages. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(4): 725-733 (2006) - 2005
- [j10]Yukihide Kohira, Atsushi Takahashi:
Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(4): 892-898 (2005) - [j9]Yukiko Kubo, Atsushi Takahashi:
A Via Assignment and Global Routing Method for 2-Layer Ball Grid Array Packages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(5): 1283-1289 (2005) - 2004
- [j8]Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh:
Optimal integer delay-budget assignment on directed acyclic graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(8): 1184-1199 (2004) - 2002
- [j7]Kengo R. Azegami, Masato Inagi, Atsushi Takahashi, Yoji Kajitani:
An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(3): 655-663 (2002) - [j6]Seiichiro Ishijima, Tetsuaki Utsumi, Tomohiro Oto, Atsushi Takahashi:
A Semi-Synchronous Circuit Design Method by Clock Tree Modification. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2596-2602 (2002) - [j5]Keiichi Kurokawa, Takuya Yasui, Yoichi Matsumura, Masahiko Toyonaga, Atsushi Takahashi:
A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2746-2755 (2002) - [j4]Makoto Saitoh, Masaaki Azuma, Atsushi Takahashi:
A Clustering Based Fast Clock Schedule Algorithm for Light Clock-Trees. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2756-2763 (2002) - 1995
- [j3]Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani:
Mixed Searching and Proper-Path-Width. Theor. Comput. Sci. 137(2): 253-268 (1995) - 1994
- [j2]Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani:
Minimal acyclic forbidden minors for the family of graphs with bounded path-width. Discret. Math. 127(1-3): 293-304 (1994) - 1992
- [j1]Atsushi Takahashi, Yoji Kajitani:
Peel-the-box: a concept of switch-box routing and tractable problems. Integr. 14(1): 33-47 (1992)
Conference and Workshop Papers
- 2019
- [c41]Shimpei Sato, Eijiro Sassa, Yuta Ukon, Atsushi Takahashi:
A Low Area Overhead Design for High-Performance General-Synchronous Circuits with Speculative Execution. ISCAS 2019: 1-5 - 2018
- [c40]Atsushi Takahashi, Shimpei Sato, Hiroki Ogura, Yu-Min Sung, Ting-Chi Wang:
Pattern Similarity Metrics for Layout Pattern Classification and Their Validity Analysis by Lithographic Responses. ISVLSI 2018: 494-497 - 2016
- [c39]Yukihide Kohira, Atsushi Takahashi, Tomomi Matsui, Chikaaki Kodama, Shigeki Nojima, Satoshi Tanaka:
Manufacturability-aware mask assignment in multiple patterning lithography. APCCAS 2016: 538-541 - [c38]Ahmed Awad, Atsushi Takahashi, Chikaaki Kodama:
A fast manufacturability aware Optical Proximity Correction (OPC) algorithm with adaptive wafer image estimation. DATE 2016: 49-54 - [c37]Takeshi Ihara, Toshiyuki Hongo, Atsushi Takahashi, Chikaaki Kodama:
Grid-based Self-Aligned Quadruple Patterning aware two dimensional routing pattern. DATE 2016: 241-244 - 2015
- [c36]Yukihide Kohira, Tomomi Matsui, Yoko Yokoyama, Chikaaki Kodama, Atsushi Takahashi, Shigeki Nojima, Satoshi Tanaka:
Fast mask assignment using positive semidefinite relaxation in LELECUT triple patterning lithography. ASP-DAC 2015: 665-670 - [c35]Takeshi Ihara, Atsushi Takahashi, Chikaaki Kodama:
Effective two-dimensional pattern generation for self-aligned double patterning. ISCAS 2015: 2141-2144 - 2014
- [c34]Yukihide Kohira, Atsushi Takahashi:
2-SAT based linear time optimum two-domain clock skew scheduling. ASP-DAC 2014: 173-178 - [c33]Ahmed Awad, Atsushi Takahashi, Satoshi Tanaka, Chikaaki Kodama:
A fast process variation and pattern fidelity aware mask optimization algorithm. ICCAD 2014: 238-245 - [c32]Tomomi Matsui, Yukihide Kohira, Chikaaki Kodama, Atsushi Takahashi:
Positive Semidefinite Relaxation and Approximation Algorithm for Triple Patterning Lithography. ISAAC 2014: 365-375 - 2013
- [c31]Chikaaki Kodama, Hirotaka Ichikawa, Koichi Nakayama, Toshiya Kotani, Shigeki Nojima, Shoji Mimotogi, Shinji Miyamoto, Atsushi Takahashi:
Self-Aligned Double and Quadruple Patterning-aware grid routing with hotspots control. ASP-DAC 2013: 267-272 - [c30]Atsushi Takahashi:
Dawn of computer-aided design: from graph-theory to place and route. ISPD 2013: 58 - 2012
- [c29]Yukihide Kohira, Atsushi Takahashi:
An any-angle routing method using quasi-Newton method. ASP-DAC 2012: 145-150 - 2011
- [c28]Yiqiang Sheng, Atsushi Takahashi, Shuichi Ueno:
RRA-based multi-objective optimization to mitigate the worst cases of placement. ASICON 2011: 329-332 - [c27]Yiqiang Sheng, Atsushi Takahashi, Shuichi Ueno:
Relay-Race Algorithm: A Novel Heuristic Approach to VLSI/PCB Placement. ISVLSI 2011: 96-101 - 2010
- [c26]Yukihide Kohira, Atsushi Takahashi:
CAFE router: a fast connectivity aware multiple nets routing algorithm for routing grid with obstacles. ASP-DAC 2010: 281-286 - 2009
- [c25]Yukihide Kohira, Suguru Suehiro, Atsushi Takahashi:
A fast longer path algorithm for routing grid with obstacles using biconnectivity based length upper bound. ASP-DAC 2009: 600-605 - 2008
- [c24]Yoichi Tomioka, Atsushi Takahashi:
A semi-monotonic routing method for fanin type Ball Grid Array packages. APCCAS 2008: 1550-1553 - [c23]Yukihide Kohira, Shuhei Tani, Atsushi Takahashi:
Minimization of delay insertion in clock period improvement in general-synchronous framework. APCCAS 2008: 1680-1683 - [c22]Yoichi Tomioka, Atsushi Takahashi:
Routability driven modification method of monotonic via assignment for 2-layer Ball Grid Array packages. ASP-DAC 2008: 238-243 - [c21]Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi:
ILP-based optimization of time-multiplexed I/O assignment for multi-FPGA systems. ISCAS 2008: 1800-1803 - 2007
- [c20]Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi:
A fast clock scheduling for peak power reduction in LSI. ACM Great Lakes Symposium on VLSI 2007: 582-587 - [c19]Yukihide Kohira, Atsushi Takahashi:
A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework. ISCAS 2007: 1795-1798 - 2006
- [c18]Bakhtiar Affendi Rosdi, Atsushi Takahashi:
Replacement of Register with Delay Element for Reducing the Area of Pipelined Circuits. APCCAS 2006: 801-804 - [c17]Bakhtiar Affendi Rosdi, Atsushi Takahashi:
Low area pipelined circuits by multi-clock cycle paths and clock scheduling. ASP-DAC 2006: 260-265 - [c16]Yoichi Tomioka, Atsushi Takahashi:
Monotonic parallel and orthogonal routing for single-layer ball grid array packages. ASP-DAC 2006: 642-647 - [c15]Yukihide Kohira, Chikaaki Kodama, Kunihiro Fujiyoshi, Atsushi Takahashi:
Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems. ISCAS 2006 - 2005
- [c14]Yukiko Kubo, Atsushi Takahashi:
A global routing method for 2-layer ball grid array packages. ISPD 2005: 36-43 - 2004
- [c13]Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh:
Incremental Timing Budget Management in Programmable Systems. ERSA 2004: 240-246 - 2003
- [c12]Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh:
Optimal integer delay budgeting on directed acyclic graphs. DAC 2003: 920-925 - 2002
- [c11]Hidetoshi Matsumura, Atsushi Takahashi:
Delay variation tolerant clock scheduling for semi-synchronous circuits. APCCAS (1) 2002: 165-170 - 2001
- [c10]Makoto Saitoh, Masaaki Azuma, Atsushi Takahashi:
Clustering based fast clock scheduling for light clock-tree. DATE 2001: 240-245 - 2000
- [c9]Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui, Atsushi Takahashi:
A practical clock tree synthesis for semi-synchronous circuits. ISPD 2000: 159-164 - [c8]Yoji Kajitani, Atsushi Takahashi, Kengo R. Azegami, Shigetoshi Nakatake:
Partition, Packing and Clock Distribution-A New Paradigm of Physical Design. VLSI Design 2000: 11 - 1999
- [c7]Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani:
Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion. ASP-DAC 1999: 125- - [c6]Kengo R. Azegami, Atsushi Takahashi, Y. Kajitan:
Enumerating the min-cuts for applications to graph extraction under size constraints. ISCAS (6) 1999: 174-177 - 1998
- [c5]Tomonori Izumi, Atsushi Takahashi, Yoji Kajitani:
Air-Pressure-Model-Based Fast Algorithms for General Floorplan. ASP-DAC 1998: 563-570 - 1997
- [c4]Atsushi Takahashi, Yoji Kajitani:
Performance and reliability driven clock scheduling of sequential logic circuits. ASP-DAC 1997: 37-42 - [c3]Atsushi Takahashi, Kazunori Inoue, Yoji Kajitani:
Clock-tree routing realizing a clock-schedule for semi-synchronous circuits. ICCAD 1997: 260-265 - 1996
- [c2]Yasuhiro Takashima, Atsushi Takahashi, Yoji Kajitani:
Detailed-Routability of FPGAs with Extremal Switch-Block Structures. ED&TC 1996: 160-164 - 1991
- [c1]Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani:
Mixed-Searching and Proper-Path-Width. ISA 1991: 61-71
Editorship
- 2023
- [e1]Atsushi Takahashi:
Proceedings of the 28th Asia and South Pacific Design Automation Conference, ASPDAC 2023, Tokyo, Japan, January 16-19, 2023. ACM 2023, ISBN 978-1-4503-9783-4 [contents]
Coauthor Index
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