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Semantic ScholarLars Bauer
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- affiliation: Karlsruhe Institute of Technology, Germany
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Books and Theses
- 2011
[b2]Lars Bauer, Jörg Henkel:
Run-time Adaptation for Reconfigurable Embedded Processors. Springer 2011, ISBN 978-1-4419-7411-2, pp. I-XXI, 1-223- 2009
- [b1]Lars Bauer:
RISPP: a run-time adaptive reconfigurable embedded processor. Karlsruhe Institute of Technology, 2009
Journal Articles
- 2019
- [j20]Farzad Samie
, Lars Bauer, Jörg Henkel:
From Cloud Down to Things: An Overview of Machine Learning in Internet of Things. IEEE Internet of Things Journal 6(3): 4921-4934 (2019) - [j19]Farzad Samie, Vasileios Tsoutsouras, Lars Bauer, Sotirios Xydis, Dimitrios Soudris, Jörg Henkel:
Oops: Optimizing Operation-mode Selection for IoT Edge Devices. ACM Trans. Internet Techn. 19(2): 22:1-22:21 (2019) - 2018
- [j18]Farzad Samie, Vasileios Tsoutsouras, Lars Bauer, Sotirios Xydis, Dimitrios Soudris, Jörg Henkel:
Distributed Trade-Based Edge Device Management in Multi-Gateway IoT. TCPS 2(3): 17:1-17:25 (2018) - [j17]Enrico Rossi, Marvin Damschen, Lars Bauer, Giorgio C. Buttazzo, Jörg Henkel:
Preemption of the Partial Reconfiguration Process to Enable Real-Time Computing With FPGAs. TRETS 11(2): 10:1-10:24 (2018) - 2017
- [j16]Marvin Damschen, Lars Bauer, Jörg Henkel:
CoRQ: Enabling Runtime Reconfiguration Under WCET Guarantees for Real-Time Systems. Embedded Systems Letters 9(3): 77-80 (2017) - [j15]Hongyan Zhang, Lars Bauer, Michael A. Kochte, Eric Schneider, Hans-Joachim Wunderlich, Jörg Henkel:
Aging Resilience and Fault Tolerance in Runtime Reconfigurable Architectures. IEEE Trans. Computers 66(6): 957-970 (2017) - [j14]Marvin Damschen, Lars Bauer, Jörg Henkel:
Timing Analysis of Tasks on Runtime Reconfigurable Processors. IEEE Trans. VLSI Syst. 25(1): 294-307 (2017) - [j13]Artjom Grudnitsky, Lars Bauer, Jörg Henkel:
Efficient Partial Online Synthesis of Special Instructions for Reconfigurable Processors. IEEE Trans. VLSI Syst. 25(2): 594-607 (2017) - 2016
- [j12]Stefan Wildermann, Michael Bader, Lars Bauer, Marvin Damschen, Dirk Gabriel, Michael Gerndt, Michael Glaß, Jörg Henkel, Johny Paul, Alexander Pöppl, Sascha Roloff, Tobias Schwarzer, Gregor Snelting, Walter Stechele, Jürgen Teich, Andreas Weichslgartner, Andreas Zwinkau:
Invasive computing for timing-predictable stream processing on MPSoCs. it - Information Technology 58(6): 267-280 (2016) - [j11]Santiago Pagani, Lars Bauer, Qingqing Chen, Elisabeth Glocker, Frank Hannig, Andreas Herkersdorf, Heba Khdr, Anuj Pathania, Ulf Schlichtmann, Doris Schmitt-Landsiedel, Mark Sagi, Éricles Rodrigues Sousa, Philipp Wagner, Volker Wenzel, Thomas Wild, Jörg Henkel:
Dark silicon management: an integrated and coordinated cross-layer approach. it - Information Technology 58(6): 297-307 (2016) - [j10]Marvin Damschen, Lars Bauer, Jörg Henkel:
Extending the WCET Problem to Optimize for Runtime-Reconfigurable Processors. TACO 13(4): 45:1-45:24 (2016) - [j9]Fazal Hameed, Lars Bauer, Jörg Henkel:
Architecting On-Chip DRAM Cache for Simultaneous Miss Rate and Latency Reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 35(4): 651-664 (2016) - 2015
- [j8]Lars Bauer, Jörg Henkel, Andreas Herkersdorf, Michael A. Kochte, Johannes Maximilian Kühn, Wolfgang Rosenstiel, Thomas Schweizer, Stefan Wallentowitz, Volker Wenzel, Thomas Wild, Hans-Joachim Wunderlich, Hongyan Zhang:
Adaptive multi-layer techniques for increased system dependability. it - Information Technology 57(3): 149-158 (2015) - [j7]Johny Paul, Walter Stechele, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat, Manfred Kröhnert, Tamim Asfour, Éricles Rodrigues Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Artjom Grudnitsky, Lars Bauer, Jörg Henkel:
Resource-awareness on heterogeneous MPSoCs for image processing. Journal of Systems Architecture - Embedded Systems Design 61(10): 668-680 (2015) - [j6]Muhammad Usman Karim Khan, Muhammad Shafique, Lars Bauer, Jörg Henkel:
Multicast FullHD H.264 Intra Video Encoder Architecture. IEEE Trans. on CAD of Integrated Circuits and Systems 34(12): 2049-2053 (2015) - 2014
- [j5]Jörg Henkel, Lars Bauer, Artjom Grudnitsky, Hongyan Zhang:
Adaptive embedded computing with i-core. SIGBED Review 11(3): 20-21 (2014) - [j4]Muhammad Shafique, Lars Bauer, Jörg Henkel:
Adaptive Energy Management for Dynamically Reconfigurable Processors. IEEE Trans. on CAD of Integrated Circuits and Systems 33(1): 50-63 (2014) - 2013
- [j3]Lars Bauer, Claus Braun, Michael E. Imhof, Michael A. Kochte, Eric Schneider, Hongyan Zhang, Jörg Henkel, Hans-Joachim Wunderlich:
Test Strategies for Reliable Runtime Reconfigurable Architectures. IEEE Trans. Computers 62(8): 1494-1507 (2013) - 2010
- [j2]Muhammad Shafique, Lars Bauer, Jörg Henkel:
Optimizing the H.264/AVC Video Encoder Application Structure for Reconfigurable and Application-Specific Platforms. Signal Processing Systems 60(2): 183-210 (2010) - 2008
- [j1]Lars Bauer, Muhammad Shafique, Jörg Henkel:
Efficient Resource Utilization for an Extensible Processor Through Dynamic Instruction Set Adaptation. IEEE Trans. VLSI Syst. 16(10): 1295-1308 (2008)
Conference and Workshop Papers
- 2019
- [c56]Manolis Katsaragakis, Dimosthenis Masouros, Vasileios Tsoutsouras, Farzad Samie, Lars Bauer, Jörg Henkel, Dimitrios Soudris:
DMRM: Distributed Market-Based Resource Management of Edge Computing Systems. DATE 2019: 1391-1396 - [c55]Lars Bauer, Marvin Damschen, Dirk Ziegenbein, Arne Hamann, Alessandro Biondi, Giorgio C. Buttazzo, Jörg Henkel:
Analyses and architectures for mixed-critical systems: industry trends and research perspective. EMSOFT Companion 2019: 13:1-13:2 - 2018
- [c54]Farzad Samie, Sebastian Paul, Lars Bauer, Jörg Henkel:
Highly efficient and accurate seizure prediction on constrained IoT devices. DATE 2018: 955-960 - 2017
- [c53]Jörg Henkel, Santiago Pagani, Hussam Amrouch, Lars Bauer, Farzad Samie:
Ultra-low power and dependability for IoT devices (Invited paper for IoT technologies). DATE 2017: 954-959 - [c52]Alexander Pöppl, Marvin Damschen, Florian Schmaus, Andreas Fried, Manuel Mohr, Matthias Blankertz, Lars Bauer, Jörg Henkel, Wolfgang Schröder-Preikschat, Michael Bader:
Shallow Water Waves on a Deep Technology Stack: Accelerating a Finite Volume Tsunami Model Using Reconfigurable Hardware in Invasive Computing. Euro-Par Workshops 2017: 676-687 - [c51]Tanja Harbaum, Christoph Schade, Marvin Damschen, Carsten Tradowsky, Lars Bauer, Jörg Henkel, Jürgen Becker:
Auto-SI: An adaptive reconfigurable processor with run-time loop detection and acceleration. SoCC 2017: 153-158 - 2016
- [c50]Farzad Samie, Lars Bauer, Jörg Henkel:
IoT technologies for embedded computing: a survey. CODES+ISSS 2016: 8:1-8:10 - [c49]Farzad Samie, Vasileios Tsoutsouras, Sotirios Xydis, Lars Bauer, Dimitrios Soudris, Jörg Henkel:
Distributed QoS management for internet of things under resource constraints. CODES+ISSS 2016: 9:1-9:10 - [c48]Hongyan Zhang, Lars Bauer, Jörg Henkel:
Resource budgeting for reliability in reconfigurable architectures. DAC 2016: 111:1-111:6 - [c47]Farzad Samie, Vasileios Tsoutsouras, Lars Bauer, Sotirios Xydis, Dimitrios Soudris, Jörg Henkel:
Computation offloading and resource allocation for low-power IoT edge devices. WF-IoT 2016: 7-12 - 2015
- [c46]Farzad Samie, Lars Bauer, Jörg Henkel:
An approximate compressor for wearable biomedical healthcare monitoring systems. CODES+ISSS 2015: 133-142 - [c45]Farzad Samie, Lars Bauer, Chih-Ming Hsieh, Jörg Henkel:
Online binding of applications to multiple clock domains in shared FPGA-based systems. DATE 2015: 25-30 - [c44]Sebastian Kobbe, Lars Bauer, Jörg Henkel:
Adaptive on-the-fly application performance modeling for many cores. DATE 2015: 730-735 - [c43]Lars Bauer, Artjom Grudnitsky, Marvin Damschen, Srinivas Rao Kerekare, Jörg Henkel:
Floating point acceleration for stream processing applications in dynamically reconfigurable processors. ESTImedia 2015: 1-2 - [c42]Hongyan Zhang, Michael A. Kochte, Eric Schneider, Lars Bauer, Hans-Joachim Wunderlich, Jörg Henkel:
STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable Architectures. ICCAD 2015: 38-45 - 2014
- [c41]Artjom Grudnitsky, Lars Bauer, Jörg Henkel:
COREFAB: Concurrent reconfigurable fabric utilization in heterogeneous multi-core systems. CASES 2014: 5:1-5:10 - [c40]Martin Haaß, Lars Bauer, Jörg Henkel:
Automatic custom instruction identification in memory streaming algorithms. CASES 2014: 6:1-6:9 - [c39]Hongyan Zhang, Michael A. Kochte, Michael E. Imhof, Lars Bauer, Hans-Joachim Wunderlich, Jörg Henkel:
GUARD: GUAranteed Reliability in Dynamically Reconfigurable Systems. DAC 2014: 32:1-32:6 - [c38]Fazal Hameed, Lars Bauer, Jörg Henkel:
Reducing Latency in an SRAM/DRAM Cache Hierarchy via a Novel Tag-Cache Architecture. DAC 2014: 37:1-37:6 - [c37]Jörg Henkel, Lars Bauer, Hongyan Zhang, Semeen Rehman, Muhammad Shafique:
Multi-Layer Dependability: From Microarchitecture to Application Level. DAC 2014: 47:1-47:6 - [c36]Artjom Grudnitsky, Lars Bauer, Jörg Henkel:
MORP: makespan optimization for processors with an embedded reconfigurable fabric. FPGA 2014: 127-136 - 2013
- [c35]Fazal Hameed, Lars Bauer, Jörg Henkel:
Simultaneously optimizing DRAM cache hit latency and miss rate via novel set mapping policies. CASES 2013: 11:1-11:10 - [c34]Manuel Mohr, Artjom Grudnitsky, Tobias Modschiedler, Lars Bauer, Sebastian Hack, Jörg Henkel:
Hardware acceleration for programs in SSA form. CASES 2013: 14:1-14:10 - [c33]Fazal Hameed, Lars Bauer, Jörg Henkel:
Reducing inter-core cache contention with an adaptive bank mapping policy in DRAM cache. CODES+ISSS 2013: 1:1-1:8 - [c32]Jörg Henkel, Lars Bauer, Nikil D. Dutt, Puneet Gupta, Sani R. Nassif, Muhammad Shafique, Mehdi Baradaran Tahoori, Norbert Wehn:
Reliable on-chip systems in the nano-era: lessons learnt and future trends. DAC 2013: 99:1-99:10 - [c31]Fazal Hameed, Lars Bauer, Jörg Henkel:
Adaptive cache management for a combined SRAM and DRAM cache hierarchy for multi-cores. DATE 2013: 77-82 - [c30]Muhammad Usman Karim Khan, Jan Micha Borrmann, Lars Bauer, Muhammad Shafique, Jörg Henkel:
An H.264 Quad-FullHD low-latency intra video encoder. DATE 2013: 115-120 - [c29]Hongyan Zhang, Lars Bauer, Michael A. Kochte, Eric Schneider, Claus Braun, Michael E. Imhof, Hans-Joachim Wunderlich, Jörg Henkel:
Module diversification: Fault tolerance and aging mitigation for runtime reconfigurable architectures. ITC 2013: 1-10 - 2012
- [c28]Lars Bauer, Claus Braun, Michael E. Imhof, Michael A. Kochte, Hongyan Zhang, Hans-Joachim Wunderlich, Jörg Henkel:
OTERA: Online test strategies for reliable reconfigurable architectures - Invited paper for the AHS-2012 special session "Dependability by reconfigurable hardware". AHS 2012: 38-45 - [c27]Jörg Henkel, Andreas Herkersdorf, Lars Bauer, Thomas Wild, Michael Hübner, Ravi Kumar Pujari, Artjom Grudnitsky, Jan Heisswolf, Aurang Zaib, Benjamin Vogel, Vahid Lari, Sebastian Kobbe:
Invasive manycore architectures. ASP-DAC 2012: 193-200 - [c26]Fazal Hameed, Lars Bauer, Jörg Henkel:
Dynamic cache management in multi-core architectures through run-time adaptation. DATE 2012: 485-490 - [c25]Artjom Grudnitsky, Lars Bauer, Jörg Henkel:
Partial online-synthesis for mixed-grained reconfigurable architectures. DATE 2012: 1555-1560 - [c24]Lars Bauer, Artjom Grudnitsky, Muhammad Shafique, Jörg Henkel:
PATS: A Performance Aware Task Scheduler for Runtime Reconfigurable Processors. FCCM 2012: 208-215 - [c23]Mohamed Abdelfattah, Lars Bauer, Claus Braun, Michael E. Imhof, Michael A. Kochte, Hongyan Zhang, Jörg Henkel, Hans-Joachim Wunderlich:
Transparent structural online test for reconfigurable systems. IOLTS 2012: 37-42 - 2011
- [c22]Lars Bauer, Muhammad Shafique, Jörg Henkel:
Concepts, architectures, and run-time systems for efficient and adaptive reconfigurable processors. AHS 2011: 80-87 - [c21]Jörg Henkel, Lars Bauer, Joachim Becker, Oliver Bringmann, Uwe Brinkschulte, Samarjit Chakraborty, Michael Engel, Rolf Ernst, Hermann Härtig, Lars Hedrich, Andreas Herkersdorf, Rüdiger Kapitza, Daniel Lohmann, Peter Marwedel, Marco Platzner, Wolfgang Rosenstiel, Ulf Schlichtmann, Olaf Spinczyk, Mehdi Baradaran Tahoori, Jürgen Teich, Norbert Wehn, Hans-Joachim Wunderlich:
Design and architectures for dependable embedded systems. CODES+ISSS 2011: 69-78 - [c20]Sebastian Kobbe, Lars Bauer, Daniel Lohmann, Wolfgang Schröder-Preikschat, Jörg Henkel:
DistRM: distributed resource management for on-chip many-core systems. CODES+ISSS 2011: 119-128 - [c19]Waheed Ahmed, Muhammad Shafique, Lars Bauer, Jörg Henkel:
Adaptive resource management for simultaneous multitasking in mixed-grained reconfigurable multi-core processors. CODES+ISSS 2011: 365-374 - [c18]Muhammad Shafique, Lars Bauer, Waheed Ahmed, Jörg Henkel:
Minority-Game-based resource allocation for run-time reconfigurable multi-core processors. DATE 2011: 1261-1266 - [c17]Waheed Ahmed, Muhammad Shafique, Lars Bauer, Jörg Henkel:
mRTS: Run-time system for reconfigurable processors with multi-grained instruction-set extensions. DATE 2011: 1554-1559 - [c16]Waheed Ahmed, Muhammad Shafique, Lars Bauer, Manuel Hammerich, Jörg Henkel, Jürgen Becker:
Run-Time Resource Allocation for Simultaneous Multi-tasking in Multi-core Reconfigurable Processors. FCCM 2011: 29-32 - 2010
- [c15]Ralf König, Lars Bauer, Timo Stripf, Muhammad Shafique, Waheed Ahmed, Jürgen Becker, Jörg Henkel:
KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture. DATE 2010: 819-824 - [c14]Muhammad Shafique, Lars Bauer, Jörg Henkel:
enBudget: A Run-Time Adaptive Predictive Energy-Budgeting scheme for energy-aware Motion Estimation in H.264/MPEG-4 AVC video encoder. DATE 2010: 1725-1730 - [c13]Muhammad Shafique, Lars Bauer, Jörg Henkel:
Selective instruction set muting for energy-aware adaptive processors. ICCAD 2010: 353-360 - 2009
- [c12]Lars Bauer, Muhammad Shafique, Jörg Henkel:
MinDeg: a performance-guided replacement policy for run-time reconfigurable accelerators. CODES+ISSS 2009: 335-342 - [c11]Lars Bauer, Muhammad Shafique, Jörg Henkel:
Cross-architectural design space exploration tool for reconfigurable processors. DATE 2009: 958-963 - [c10]Muhammad Shafique, Lars Bauer, Jörg Henkel:
A parallel approach for high performance hardware design of intra prediction in H.264/AVC Video Codec. DATE 2009: 1434-1439 - [c9]Lars Bauer, Muhammad Shafique, Jörg Henkel:
RISPP: A run-time adaptive reconfigurable embedded processor. FPL 2009: 725-726 - [c8]Muhammad Shafique, Lars Bauer, Jörg Henkel:
REMiS: Run-time energy minimization scheme in a reconfigurable processor with dynamic power-gated instruction set. ICCAD 2009: 55-62 - 2008
- [c7]Lars Bauer, Muhammad Shafique, Jörg Henkel:
Run-time instruction set selection in a transmutable embedded processor. DAC 2008: 56-61 - [c6]Lars Bauer, Muhammad Shafique, Stephanie Kreutz, Jörg Henkel:
Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set. DATE 2008: 752-757 - [c5]Lars Bauer, Muhammad Shafique, Jörg Henkel:
A computation- and communication- infrastructure for modular special instructions in a dynamically reconfigurable processor. FPL 2008: 203-208 - [c4]Muhammad Shafique, Lars Bauer, Jörg Henkel:
3-tier dynamically adaptive power-aware motion estimator for h.264/AVC video encoding. ISLPED 2008: 147-152 - 2007
- [c3]Lars Bauer, Muhammad Shafique, Simon Kramer, Jörg Henkel:
RISPP: Rotating Instruction Set Processing Platform. DAC 2007: 791-796 - [c2]Muhammad Shafique, Lars Bauer, Jörg Henkel:
An Optimized Application Architecture of the H.264 Video Encoder for Application Specific Platforms. ESTImedia 2007: 119-124 - [c1]Lars Bauer, Muhammad Shafique, Dirk Teufel, Jörg Henkel:
A Self-Adaptive Extensible Embedded Processor. SASO 2007: 344-350
Coauthor Index
[b2] [j20] [j19] [j18] [j17] [j16] [j15] [j14] [j13] [j12] [j11] [j10] [j9] [j8] [j7] [j6] [j5] [j4] [j3] [j2] [j1] [c56] [c55] [c54] [c53] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [c34] [c33] [c32] [c31] [c30] [c29] [c28] [c27] [c26] [c25] [c24] [c23] [c22] [c21] [c20] [c19] [c18] [c17] [c16] [c15] [c14] [c13] [c12] [c11] [c10] [c9] [c8] [c7] [c6] [c5] [c4] [c3] [c2] [c1]
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