Xun Sun

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Rajesh Pamula 0001

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Publications

2022
[j37]
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Chi-Hsiang Huang, Yidong Chen, Xun Sun, Arindam Mandal, Venkata Rajesh Pamula, Nasser A. Kurd, Visvesh S. Sathe:
Improving SIMO-Regulated Digital SoC Energy Efficiencies Through Adaptive Clocking and Concurrent Domain Control. IEEE J. Solid State Circuits 57(1): 90-102 (2022)
2021
[c25]
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  - conf/isscc/HuangSCPMS21
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Chi-Hsiang Huang, Xun Sun, Yidong Chen, Rajesh Pamula, Arindam Mandal, Visvesh Sathe:
A Single-Inductor 4-Output SoC with Dynamic Droop Allocation and Adaptive Clocking for Enhanced Performance and Energy Efficiency in 65nm CMOS. ISSCC 2021: 416-418
2020
[c24]
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  - conf/vlsic/SunB00P020
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Xun Sun, Akshat Boora, Rajesh Pamula, Chi-Hsiang Huang, Diego Peña-Colaiocco, Visvesh S. Sathe:
Model Predictive Control of an Integrated Buck Converter for Digital SoC Domains in 65nm CMOS. VLSI Circuits 2020: 1-2
[c23]
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Xun Sun, Akshat Boora, Rajesh Pamula, Chi-Hsiang Huang, Diego Peña-Colaiocco, Visvesh S. Sathe:
UniCaP-2: Phase-Locked Adaptive Clocking with Rapid Clock Cycle Recovery in 65nm CMOS. VLSI Circuits 2020: 1-2
2019
[j28]
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Xun Sun, Fahim ur Rahman, Venkata Rajesh Pamula, Sung Kim, Xi Li, Naveen John, Visvesh S. Sathe:
An All-Digital Fused PLL-Buck Architecture for 82% Average V_dd-Margin Reduction in a 0.6-to-1.0-V Cortex-M0 Processor. IEEE J. Solid State Circuits 54(11): 3215-3225 (2019)
[c19]
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Xun Sun, Akshat Boora, Wenbing Zhang, Venkata Rajesh Pamula, Visvesh Sathe:
A 0.6-to-1.1V Computationally Regulated Digital LDO with 2.79-Cycle Mean Settling Time and Autonomous Runtime Gain Tracking in 65nm CMOS. ISSCC 2019: 230-232
[c18]
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  - conf/isscc/RahmanPBSS19
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Fahim ur Rahman, Rajesh Pamula, Akshat Boora, Xun Sun, Visvesh Sathe:
Computationally Enabled Total Energy Minimization Under Performance Requirements for a Voltage-Regulated 0.38-to-0.58V Microprocessor in 65nm CMOS. ISSCC 2019: 312-314
2018
[c17]
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Xun Sun, Sung Kim, Fahim ur Rahman, Venkata Rajesh Pamula, Xi Li, Naveen John, Visvesh S. Sathe:
A combined all-digital PLL-buck slack regulation system with autonomous CCM/DCM transition control and 82% average voltage-margin reduction in a 0.6-to-1.0V cortex-M0 processor. ISSCC 2018: 302-304
[c16]
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  - conf/vlsic/PamulaSKRZS18
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Rajesh Pamula, Xun Sun, Sung Kim, Fahim ur Rahman, Baosen Zhang, Visvesh S. Sathe:
An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS. VLSI Circuits 2018: 1-2

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