Insup Shin

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▷ joint publications with Youngsoo Shin

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Publications

2016
[j7]
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Insup Shin, Jae-Joon Kim, Yu-Shiang Lin, Youngsoo Shin:
One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 600-612 (2016)
2015
[j6]
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  - journals/tcas/ShinKS15
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Insup Shin, Jae-Joon Kim, Youngsoo Shin:
Aggressive Voltage Scaling Through Fast Correction of Multiple Errors With Seamless Pipeline Operation. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(2): 468-477 (2015)
2014
[j5]
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Youngsoo Shin, Insup Shin, Donkyu Baek, Duckhwan Kim, Seungwhun Paik:
HAPL: Heterogeneous Array of Programmable Logic Using Selective Mask Patterning. IEEE Trans. Circuits Syst. I Regul. Pap. 61-I(1): 146-159 (2014)
[c8]
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  - conf/aspdac/ShinKS14
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Insup Shin, Jae-Joon Kim, Youngsoo Shin:
Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling. ASP-DAC 2014: 179-184
2013
[j4]
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  - journals/jcsc/BaekSS13
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Donkyu Baek, Insup Shin, Youngsoo Shin:
Accurate gate delay Extraction for Timing Analysis of Body-Biased Circuits. J. Circuits Syst. Comput. 22(8) (2013)
[c7]
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Insup Shin, Jae-Joon Kim, Yu-Shiang Lin, Youngsoo Shin:
A pipeline architecture with 1-cycle timing error correction for low voltage operations. ISLPED 2013: 199-204
2012
[j3]
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  - journals/tcad/SeomunSS12
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Jun Seomun, Insup Shin, Youngsoo Shin:
Synthesis of Active-Mode Power-Gating Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(3): 391-403 (2012)
[j2]
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  - journals/tvlsi/ShinPSS12
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Insup Shin, Seungwhun Paik, Dongwan Shin, Youngsoo Shin:
HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures. IEEE Trans. Very Large Scale Integr. Syst. 20(4): 593-604 (2012)
[c6]
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  - conf/fpt/ShinBS12
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Insup Shin, Donkyu Baek, Youngsoo Shin:
Introducing irregularity to routing architecture of structured ASIC for better routability. FPT 2012: 224-228
[c5]
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  - conf/icicdt/BaekSS12
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Donkyu Baek, Insup Shin, Youngsoo Shin:
Gate delay modeling for static timing analysis of body-biased circuits. ICICDT 2012: 1-4
2011
[c4]
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  - conf/aspdac/BaekSPS11
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Donkyu Baek, Insup Shin, Seungwhun Paik, Youngsoo Shin:
Selectively patterned masks: Structured ASIC with asymptotically ASIC performance. ASP-DAC 2011: 376-381
2010
[j1]
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  - journals/tcad/PaikSKS10
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Seungwhun Paik, Insup Shin, Taewhan Kim, Youngsoo Shin:
HLS-l: A High-Level Synthesis Framework for Latch-Based Architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 657-670 (2010)
[c3]
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Jun Seomun, Insup Shin, Youngsoo Shin:
Synthesis and implementation of active mode power gating circuits. DAC 2010: 487-492
2009
[c2]
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  - conf/dac/ShinPS09
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Insup Shin, Seungwhun Paik, Youngsoo Shin:
Register allocation for high-level synthesis using dual supply voltages. DAC 2009: 937-942
[c1]
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Seungwhun Paik, Insup Shin, Youngsoo Shin:
HLS-l: High-level synthesis of high performance latch-based circuits. DATE 2009: 1112-1117

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