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Kanishka Lahiri
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Publications
- 2010
- [j9]Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Variation-Aware System-Level Power Analysis. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1173-1184 (2010) - 2009
- [j8]Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Variation-Tolerant Dynamic Power Management at the System-Level. IEEE Trans. Very Large Scale Integr. Syst. 17(9): 1220-1232 (2009) - 2008
- [j7]Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication. IEEE Trans. Very Large Scale Integr. Syst. 16(10): 1413-1426 (2008) - 2007
- [c27]Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
System-on-Chip Power Management Considering Leakage Power Variations. DAC 2007: 877-882 - 2006
- [c20]Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Integrated data relocation and bus reconfiguration for adaptive system-on-chip platforms. DATE 2006: 728-733 - [c19]Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Considering process variations during system-level power analysis. ISLPED 2006: 342-345 - 2005
- [c18]Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology. DAC 2005: 571-574 - 2004
- [j5]Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey:
Design of high-performance system-on-chips using communication architecture tuners. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5): 620-636 (2004) - [j4]Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Efficient power profiling for battery-driven embedded system design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(6): 919-932 (2004) - [j3]Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Design space exploration for optimizing on-chip communication architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(6): 952-961 (2004) - [c13]Krishna Sekar, Kanishka Lahiri, Sujit Dey:
Configurable Platforms With Dynamic Platform Management: An Efficient Alternative to Application-Specific System-on-Chips. VLSI Design 2004: 307- - 2003
- [c12]Krishna Sekar, Kanishka Lahiri, Sujit Dey:
Dynamic Platform Management for Configurable Platform-Based System-on-Chips. ICCAD 2003: 641-649 - 2002
- [j2]Kanishka Lahiri, Sujit Dey, Anand Raghunathan:
Communication-Based Power Management. IEEE Des. Test Comput. 19(4): 118-130 (2002) - [c11]Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Fast system-level power profiling for battery-efficient system design. CODES 2002: 157-162 - [c10]Kanishka Lahiri, Sujit Dey, Anand Raghunathan:
Communication architecture based power management for battery efficient system design. DAC 2002: 691-696 - [c9]Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Battery-efficient architecture for an 802.11 MAC processor. ICC 2002: 669-674 - [c8]Kanishka Lahiri, Anand Raghunathan, Sujit Dey, Debashis Panigrahi:
Embedded Tutorial: Battery-Driven System Design: A New Frontier in Low Power Design. ASP-DAC/VLSI Design 2002: 261-267 - 2001
- [j1]Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
System-level performance analysis for designing on-chipcommunication architectures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(6): 768-783 (2001) - [c6]Kanishka Lahiri, Sujit Dey, Anand Raghunathan:
Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures. VLSI Design 2001: 29-35 - [c5]Debashis Panigrahi, Sujit Dey, Ramesh R. Rao, Kanishka Lahiri, Carla-Fabiana Chiasserini, Anand Raghunathan:
Battery Life Estimation of Mobile Embedded Systems. VLSI Design 2001: 57-63 - 2000
- [c4]Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit Dey:
Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips. DAC 2000: 513-518 - [c3]Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Efficient Exploration of the SoC Communication Architecture Design Space. ICCAD 2000: 424-430 - [c2]Kanishka Lahiri, Sujit Dey, Anand Raghunathan:
Performance Analysis of Systems with Multi-Channel Communication Architectures. VLSI Design 2000: 530-537 - 1999
- [c1]Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
Fast performance analysis of bus-based system-on-chip communication architectures. ICCAD 1999: 566-573
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