Roberto Gioiosa

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Carlos Boneti

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Publications

2013
[j6]
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Alessandro Morari, Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero:
SMT Malleability in IBM POWER5 and POWER6 Processors. IEEE Trans. Computers 62(4): 813-826 (2013)
2011
[j4]
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  - journals/esticas/JimenezCGVBKCIBB11
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Víctor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose:
Characterizing Power and Temperature Behavior of POWER6-Based System. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 228-241 (2011)
2010
[c15]
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  - conf/IEEEpact/JimenezCGVBKCIBB10
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Víctor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose:
Power and thermal characterization of POWER6 system. PACT 2010: 7-18
2008
[c7]
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  - conf/arcs/BonetiCGV08
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Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero:
Soft Real-Time Scheduling on SMT Processors with Explicit Resource Allocation. ARCS 2008: 173-187
[c6]
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  - conf/ipps/BonetiGCCLV08
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Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, Julita Corbalán, Jesús Labarta, Mateo Valero:
Balancing HPC applications through smart allocation of resources in MT processors. IPDPS 2008: 1-12
[c5]
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  - conf/isca/BonetiCGBCV08
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Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Chen-Yong Cher, Mateo Valero:
Software-Controlled Priority Characterization of POWER5 Processor. ISCA 2008: 415-426
[c3]
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  - conf/sc/BonetiGCV08
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Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, Mateo Valero:
A dynamic scheduler for balancing HPC applications. SC 2008: 41

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