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Jianmin Zhang
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Publications
- 2024
- [j36]Bo Wang, Sheng Ma, Shengbai Luo, Lizhou Wu, Jianmin Zhang, Chunyuan Zhang, Tiejun Li:
SparGD: A Sparse GEMM Accelerator with Dynamic Dataflow. ACM Trans. Design Autom. Electr. Syst. 29(2): 26:1-26:32 (2024) - 2023
- [j31]Siqing Fu, Tiejun Li, Chunyuan Zhang, Hanqing Li, Sheng Ma, Jianmin Zhang, Ruiyi Zhang, Lizhou Wu:
RHS-TRNG: A Resilient High-Speed True Random Number Generator Based on STT-MTJ Device. IEEE Trans. Very Large Scale Integr. Syst. 31(10): 1578-1591 (2023) - [c67]Xiao Yi, Bo Wang, Shengbai Luo, Tiejun Li, Lizhou Wu, Jianmin Zhang, Kenli Li, Sheng Ma:
A Hybrid Kernel Pruning Approach for Efficient and Accurate CNNs. ICA3PP (7) 2023: 34-46 - [c66]Xiang Hou, Yuan Yuan, Sheng Ma, Rui Xu, Bo Wang, Tiejun Li, Wei Jiang, Lizhou Wu, Jianmin Zhang:
Optimizing the Parallelism of Communication and Computation in Distributed Training Platform. ICA3PP (1) 2023: 340-359 - [i4]Siqing Fu, Tiejun Li, Chunyuan Zhang, Hanqing Li, Sheng Ma, Jianmin Zhang, Ruiyi Zhang, Lizhou Wu:
RHS-TRNG: A Resilient High-Speed True Random Number Generator Based on STT-MTJ Device. CoRR abs/2312.17453 (2023) - 2021
- [c60]Tiejun Li, Jianmin Zhang, Siqing Fu, Kefan Ma:
A Variable-Way Address Translation Cache for the Exascale Supercomputer. ICA3PP (3) 2021: 231-244 - [c58]Siqing Fu, Tiejun Li, Jianmin Zhang, Sheng Ma, Sheng Liu:
MiniMCTAD: Minimalist Monte Carlo Transport Architecture Design. ISPA/BDCloud/SocialCom/SustainCom 2021: 1-10 - [c57]Jianmin Zhang, Tiejun Li, Yan Sun:
A Two-level Concurrent Address Translation Cache of High Performance Interconnect Network. ISPA/BDCloud/SocialCom/SustainCom 2021: 1183-1188 - [c55]Jianmin Zhang, Tiejun Li, Siqing Fu:
An Incomplete Unsatisfiable Cores Extracting Algorithm to Promote Routing. QRS 2021: 900-905 - 2020
- [c51]Jianmin Zhang, Tiejun Li, Kefan Ma:
Accelerating Predicate Abstraction by Minimum Unsatisfiable Cores Extraction. NCTCS 2020: 3-13 - 2019
- [c48]Jianmin Zhang, Tiejun Li, Liquan Xiao:
A Reconfigurable Address Translation Cache for Interconnect Network of High Performance Computer. HPCC/SmartCity/DSS 2019: 714-717 - 2015
- [c35]Jianmin Zhang, Tiejun Li, Sikun Li:
Application and analysis of unsatisfiable cores on circuits synthesis. ICACI 2015: 407-410 - 2013
- [c29]Tiejun Li, Jianmin Zhang, Sikun Li:
An FPGA-based Random Functional Verification Method for Cache. NAS 2013: 277-281 - 2011
- [c24]Jianmin Zhang, Weixia Xu, Jun Zhang, ShengYu Shen, Zhengbin Pang, Tiejun Li, Jun Xia, Sikun Li:
Finding First-Order Minimal Unsatisfiable Cores with a Heuristic Depth-First-Search Algorithm. IDEAL 2011: 178-185
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