Avinoam Kolodny

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Shmuel Wimer

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Publications

2015
[j45]
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Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny:
Timing-constrained power minimization in VLSI circuits by simultaneous multilayer wire spacing. Integr. 48: 116-128 (2015)
2012
[j30]
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  - journals/jco/MoiseevKW12
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Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer:
The complexity of VLSI power-delay optimization by interconnect resizing. J. Comb. Optim. 23(2): 292-300 (2012)
2011
[c42]
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  - conf/dsd/ManevichCKWW11
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Ran Manevich, Israel Cidon, Avinoam Kolodny, Isask'har Walter, Shmuel Wimer:
A Cost Effective Centralized Adaptive Routing for Networks-on-Chip. DSD 2011: 39-46
2010
[j23]
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  - journals/tcad/MoiseevKW10
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Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer:
Interconnect Bundle Sizing Under Discrete Design Rules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(10): 1650-1654 (2010)
[c31]
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Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer:
Interconnect power and delay optimization by dynamic programming in gridded design rules. ISPD 2010: 153-160
2009
[j17]
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Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer:
Power-delay optimization in VLSI microprocessors by wire spacing. ACM Trans. Design Autom. Electr. Syst. 14(4): 55:1-55:28 (2009)
2008
[j14]
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Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny:
On optimal ordering of signals in parallel wire bundles. Integr. 41(2): 253-268 (2008)
[j13]
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Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer:
Timing-aware power-optimal ordering of signals. ACM Trans. Design Autom. Electr. Syst. 13(4): 65:1-65:17 (2008)
2006
[j7]
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  - journals/tcas/WimerMMK06
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Shmuel Wimer, Shay Michaely, Konstantin Moiseev, Avinoam Kolodny:
Optimal bus sizing in migration of processor design. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(5): 1089-1100 (2006)
[c13]
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Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny:
Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing. ISCAS 2006
2004
[c6]
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  - conf/icecsys/MichaelyWK04
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Shay Michaely, Shmuel Wimer, Avinoam Kolodny:
Optimal resizing of bus wires in layout migration. ICECS 2004: 411-414

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