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Ryusuke Egawa
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Publications
- 2020
- [j17]Takashi Soga, Kenta Yamaguchi, Raghunandan Mathur, Osamu Watanabe, Akihiro Musa, Ryusuke Egawa, Hiroaki Kobayashi:
Effects of Using a Memory Stalled Core for Handling MPI Communication Overlapping in the SOR Solver on SX-ACE and SX-Aurora TSUBASA. Supercomput. Front. Innov. 7(4): 4-15 (2020) - 2019
- [j15]Kenta Yamaguchi, Takashi Soga, Yoichi Shimomura, Thorsten Reimann, Kazuhiko Komatsu, Ryusuke Egawa, Akihiro Musa, Hiroyuki Takizawa, Hiroaki Kobayashi:
Performance Evaluation of Different Implementation Schemes of an Iterative Flow Solver on Modern Vector Machines. Supercomput. Front. Innov. 6(1): 36-47 (2019) - 2017
- [j10]Ryusuke Egawa, Kazuhiko Komatsu, Shintaro Momose, Yoko Isobe, Akihiro Musa, Hiroyuki Takizawa, Hiroaki Kobayashi:
Potential of a modern vector supercomputer for practical applications: performance evaluation of SX-ACE. J. Supercomput. 73(9): 3948-3976 (2017) - [c49]Hiroyuki Takizawa, Thorsten Reimann, Kazuhiko Komatsu, Takashi Soga, Ryusuke Egawa, Akihiro Musa, Hiroaki Kobayashi:
Vectorization-Aware Loop Optimization with User-Defined Code Transformations. CLUSTER 2017: 685-692 - [c48]Ryusuke Egawa, Kazuhiko Komatsu, Yoko Isobe, Toshihiro Kato, Souya Fujimoto, Hiroyuki Takizawa, Akihiro Musa, Hiroaki Kobayashi:
Performance and Power Analysis of SX-ACE Using HP-X Benchmark Programs. CLUSTER 2017: 693-700 - 2016
- [j8]Raghunandan Mathur, Hiroshi Matsuoka, Osamu Watanabe, Akihiro Musa, Ryusuke Egawa, Hiroaki Kobayashi:
A Memory-Efficient Implementation of a Plasmonics Simulation Application on SX-ACE. Int. J. Netw. Comput. 6(2): 243-262 (2016) - 2015
- [c35]Raghunandan Mathur, Hiroshi Matsuoka, Osamu Watanabe, Akihiro Musa, Ryusuke Egawa, Hiroaki Kobayashi:
A Case Study of Memory Optimization for Migration of a Plasmonics Simulation Application to SX-ACE. CANDAR 2015: 521-527 - 2011
- [c20]Ryusuke Egawa, Yusuke Funaya, Ryu-ichi Nagaoka, Yusuke Endo, Akihiro Musa, Hiroyuki Takizawa, Hiroaki Kobayashi:
Effects of 3-D stacked vector cache on energy consumption. 3DIC 2011: 1-6 - 2010
- [c18]Ryusuke Egawa, Yusuke Funaya, Ryu-ichi Nagaoka, Akihiro Musa, Hiroyuki Takizawa, Hiroaki Kobayashi:
Design and early evaluation of a 3-D die stacked chip multi-vector processor. 3DIC 2010: 1-8 - 2009
- [c10]Yoshiei Sato, Ryu-ichi Nagaoka, Akihiro Musa, Ryusuke Egawa, Hiroyuki Takizawa, Koki Okabe, Hiroaki Kobayashi:
Performance tuning and analysis of future vector processors based on the roofline model. MEDEA@PACT 2009: 7-14 - [c9]Takashi Soga, Akihiro Musa, Youichi Shimomura, Ryusuke Egawa, Ken'ichi Itakura, Hiroyuki Takizawa, Koki Okabe, Hiroaki Kobayashi:
Performance evaluation of NEC SX-9 using real science and engineering applications. SC 2009 - 2008
- [c7]Akihiro Musa, Yoshiei Sato, Takashi Soga, Ryusuke Egawa, Hiroyuki Takizawa, Koki Okabe, Hiroaki Kobayashi:
Effects of MSHR and Prefetch Mechanisms on an On-Chip Cache of the Vector Architecture. ISPA 2008: 335-342 - [c5]Akihiro Musa, Yoshiei Sato, Takashi Soga, Koki Okabe, Ryusuke Egawa, Hiroyuki Takizawa, Hiroaki Kobayashi:
A shared cache for a chip multi vector processor. MEDEA@PACT 2008: 24-29 - 2007
- [c4]Akihiro Musa, Yoshiei Sato, Ryusuke Egawa, Hiroyuki Takizawa, Koki Okabe, Hiroaki Kobayashi:
An on-chip cache design for vector processors. MEDEA@PACT 2007: 17-23
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