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Daniel Chillet
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Publications
- 2013
- [c31]Quang-Hai Khuat, Quang-Hoa Le, Daniel Chillet, Sébastien Pillement:
Spatio-temporal scheduling for 3D reconfigurable & multiprocessor architecture. IDT 2013: 1-6 - 2012
- [c29]Robin Bonamy, Hung-Manh Pham, Sébastien Pillement, Daniel Chillet:
UPaRC - Ultra-fast power-aware reconfiguration controller. DATE 2012: 1373-1378 - 2011
- [j9]Daniel Chillet, Antoine Eiche, Sébastien Pillement, Olivier Sentieys:
Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network. J. Syst. Archit. 57(4): 340-353 (2011) - [c26]Antoine Eiche, Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
Parallel Evaluation of Hopfield Neural Networks. IJCCI (NCTA) 2011: 248-253 - [c25]Surya Narayanan, Daniel Chillet, Sébastien Pillement, Ioannis Sourdis:
Hardware OS Communication Service and Dynamic Memory Management for RSoCs. ReConFig 2011: 117-122 - [c23]Surya Narayanan, Ludovic Devaux, Daniel Chillet, Sébastien Pillement, Ioannis Sourdis:
Communication service for hardware tasks executed on dynamic and partial reconfigurable resources. VLSI-SoC 2011: 196-199 - 2010
- [j7]Ludovic Devaux, Sana Ben Sassi, Sébastien Pillement, Daniel Chillet, Didier Demigny:
Flexible Interconnection Network for Dynamically and Partially Reconfigurable Architectures. Int. J. Reconfigurable Comput. 2010: 390545:1-390545:15 (2010) - [c22]Antoine Eiche, Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
Task placement for dynamic and partial reconfigurable architecture. DASIP 2010: 228-234 - [c20]Ludovic Devaux, Sébastien Pillement, Daniel Chillet, Didier Demigny:
R2NoC: Dynamically Reconfigurable Routers for Flexible Networks on Chip. ReConFig 2010: 376-381 - [c19]Ludovic Devaux, Sébastien Pillement, Daniel Chillet, Didier Demigny:
Mesh and Fat-Tree comparison for dynamically reconfigurable applications. ReCoSoC 2010: 157-160 - 2009
- [j6]Benoît Miramond, Emmanuel Huck, François Verdier, Mohamed El Amine Benkhelifa, Bertrand Granado, Thomas LeFebvre, Mehdi Aïchouch, Jean-Christophe Prévotet, Yaset Oliva, Daniel Chillet, Sébastien Pillement:
OveRSoC: A Framework for the Exploration of RTOS for RSoC Platforms. Int. J. Reconfigurable Comput. 2009: 450607:1-450607:22 (2009) - [c18]Sébastien Pillement, Daniel Chillet, Yaset Oliva, Jean-Christophe Prévotet:
High-Level Exploration for Dynamic Reconfiguration Management. ERSA 2009: 301-302 - 2008
- [c17]Jean-Christophe Prévotet, Mohamed El Amine Benkhelifa, Bertrand Granado, Emmanuel Huck, Benoît Miramond, François Verdier, Daniel Chillet, Sébastien Pillement:
A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources. ReConFig 2008: 61-66 - 2007
- [c16]Imene Benkermi, Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
Hardware task scheduling for heterogeneous soc architectures. EUSIPCO 2007: 1653-1657 - [c15]Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
A Neural Network Model for Real-Time Scheduling on Heterogeneous SoC Architectures. IJCNN 2007: 102-107 - 2005
- [c13]François Verdier, Jean-Christophe Prévotet, Mohamed El Amine Benkhelifa, Daniel Chillet, Sébastien Pillement:
Exploring RTOS issues with a high-level model of a reconfigurable SoC platform. ReCoSoC 2005: 71-78 - 2002
- [c11]Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
A Compilation Framework for a Dynamically Reconfigurable Architecture. FPL 2002: 1058-1067 - [c10]Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
Mapping future generation mobile telecommunication applications on a dynamically reconfigurable arcidtecture. ICASSP 2002: 4194 - [c9]Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
DART: A Dynamically Reconfigurable Architecture Dealing with Future Mobile Telecommunications Constraints. IPDPS 2002 - [c8]Sébastien Pillement, Daniel Chillet, Olivier Sentieys:
Behavioral IP Specification and Integration Framework for High-Level Design Reuse. ISQED 2002: 388-393 - 2001
- [c7]Raphaël David, Daniel Chillet, Sébastien Pillement, Olivier Sentieys:
A Dynamically Reconfigurable Architecture for Low-Power Multimedia Terminals. VLSI-SOC 2001: 51-62
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