Miguel O. Arias-Estrada

◀ ▶ joint publications with Griselda Saldaña-González

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Publications

2008
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Griselda Saldaña, Miguel Arias-Estrada:
A Low-Level Image Processing Algorithms Accelerator Platform. CONIELECOMP 2008: 117-122
2007
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Griselda Saldaña, Miguel Arias-Estrada:
Compact FPGA-based systolic array architecture suitable for vision systems. Int. J. High Perform. Syst. Archit. 1(2): 124-132 (2007)
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Griselda Saldaña, Miguel Arias-Estrada:
Compact FPGA-based systolic array architecture suitable for vision systems. ITNG 2007: 1008-1013
2006
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Griselda Saldaña, Miguel Arias-Estrada:
Customizable FPGA-based architecture for video applications in real time. FPT 2006: 381-384
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Griselda Saldaña, Miguel Arias-Estrada:
Real Time FPGA-based Architecture for Video Applications. ReConFig 2006: 217-226
2005
[c12]
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Griselda Saldaña, Miguel Arias-Estrada:
FPGA-based customizable systolic architecture for image processing applications. ReConFig 2005

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