Keith A. Bowman

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Jihoon Jeong

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Publications

2019
[c37]
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Francois Atallah, Keith A. Bowman, Hoan Nguyen, Jihoon Jeong, Daniel Yingling, Yu Sun, Brad Appel, Anthony Polomik, Mahesh Harinath, Joshua Morelli, Thomas Moore, Nathaniel Reeves, Amer Cassier, Arijit Raychowdhury:
A 7nm All-Digital Unified Voltage and Frequency Regulator Based on a High-Bandwidth 2-Phase Buck Converter with Package Inductors. ISSCC 2019: 316-318
[c36]
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Keith A. Bowman, Samantak Gangopadhyay, Francois Atallah, Hoan Nguyen, Jihoon Jeong, Daniel Yingling, Anthony Polomik, Mahesh Harinath, Nathaniel Reeves, Amer Cassier, Brad Appel, Arijit Raychowdhury:
A 7nm Leakage-Current-Supply Circuit for LDO Dropout Voltage Reduction. VLSI Circuits 2019: 126-
2018
[c35]
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Hoan Nguyen, Jihoon Jeong, Francois Atallah, Marc Jansen, Anthony Polomik, Daniel Yingling, Harsha Akkaraju, Brad Appel, Rahul Nadkarni, Keith A. Bowman:
A 7NM Double-Pumped 6R6W Register File for Machine Learning Memory. VLSI Circuits 2018: 1-2
2017
[c33]
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Samantak Gangopadhyay, Saad Bin Nasir, Hoan Nguyen, Jihoon Jeong, Francois Atallah, Keith A. Bowman, Arijit Raychowdhury:
Digitally-assisted leakage current supply circuit for reducing the analog LDO minimum dropout voltage. CICC 2017: 1-4
2016
[j17]
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Keith A. Bowman, Sarthak Raina, Todd Bridges, Daniel Yingling, Hoan Nguyen, Brad Appel, Yesh Kolla, Jihoon Jeong, Francois Atallah, David Hansquine:
A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range. IEEE J. Solid State Circuits 51(1): 8-17 (2016)
2015
[c31]
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Jihoon Jeong, Francois Atallah, Hoan Nguyen, Josh Puckett, Keith A. Bowman, David Hansquine:
A 16nm configurable pass-gate bit-cell register file for quantifying the VMIN advantage of PFET versus NFET pass-gate bit cells. CICC 2015: 1-4
[c30]
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Keith A. Bowman, Sarthak Raina, Todd Bridges, Daniel Yingling, Hoan Nguyen, Brad Appel, Yesh Kolla, Jihoon Jeong, Francois Atallah, David Hansquine:
8.5 A 16nm auto-calibrating dynamically adaptive clock distribution for maximizing supply-voltage-droop tolerance across a wide operating range. ISSCC 2015: 1-3

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