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Mike Schlansker
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Publications
- 2001
- [j11]B. Ramakrishna Rau, Michael S. Schlansker:
Embedded Computer Architecture and Automation. Computer 34(4): 75-83 (2001) - [j9]Vinod Kathail, Michael S. Schlansker, B. Ramakrishna Rau:
Compiling for EPIC architectures. Proc. IEEE 89(11): 1676-1693 (2001) - 2000
- [j7]Michael S. Schlansker, B. Ramakrishna Rau:
EPIC: Explicititly Parallel Instruction Computing. Computer 33(2): 37-45 (2000) - [c16]B. Ramakrishna Rau, Michael S. Schlansker:
Embedded Computing: New Directions in Architecture and Automation. HiPC 2000: 225-244 - 1996
- [c14]Chandra Chekuri, Richard Johnson, Rajeev Motwani, B. Natarajan, B. Ramakrishna Rau, Michael S. Schlansker:
Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks. MICRO 1996: 58-67 - 1993
- [j2]Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker:
Sentinel Scheduling for VLIW and Superscalar Processors. ACM Trans. Comput. Syst. 11(4): 376-408 (1993) - 1992
- [c7]Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker:
Sentinel Scheduling for VLIW and Superscalar Processors. ASPLOS 1992: 238-247 - [c6]B. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai:
Code generation schema for modulo scheduled loops. MICRO 1992: 158-169 - [c5]B. Ramakrishna Rau, Meng Lee, Parthasarathy P. Tirumalai, Michael S. Schlansker:
Register Allocation for Software Pipelined Loops. PLDI 1992: 283-299 - 1989
- [c3]B. Ramakrishna Rau, Michael S. Schlansker, David W. L. Yen:
The Cydram 5 Stride-Insensitive Memory System. ICPP (1) 1989: 242-246 - 1982
- [c2]Pradip Bose, B. Ramakrishna Rau, Michael S. Schlansker:
Systematically derived instruction sets for high-level language support. ACM Southeast Regional Conference 1982: 73-84
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