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Chittaranjan A. Mandal
Publications
- 2018
- [i3]Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
STAIRoute: Early Global Routing using Monotone Staircases for Congestion Reduction. CoRR abs/1810.10412 (2018) - [i2]Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
Early Routability Assessment in VLSI Floorplans: A Generalized Routing Model. CoRR abs/1810.12789 (2018) - [i1]Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
Exploring the Scope of Unconstrained Via Minimization by Recursive Floorplan Bipartitioning. CoRR abs/1811.05161 (2018) - 2016
- [c49]Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
An early global routing framework for uniform wire distribution in SoCs. SoCC 2016: 139-144 - [c48]Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
A Novel EPE Aware Hybrid Global Route Planner after Floorplanning. VLSID 2016: 595-596 - 2015
- [c45]Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
A New Method for Defining Monotone Staircases in VLSI Floorplans. ISVLSI 2015: 107-112 - 2014
- [c36]Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
Global Routing Using Monotone Staircases with Minimal Bends. VLSID 2014: 369-374 - 2013
- [c33]Bapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal:
STAIRoute: Global routing using monotone staircase channels. ISVLSI 2013: 90-95 - 2012
- [c28]Bapi Kar, Susmita Sur-Kolay, Sridhar H. Rangarajan, Chittaranjan A. Mandal:
A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts. VDAT 2012: 327-336
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