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Hiroto Yasuura
- > Home > Persons > Hiroto Yasuura
Publications
- 2010
- [j28]Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura:
Code and Data Placement for Embedded Processors with Scratchpad and Cache Memories. J. Signal Process. Syst. 60(2): 211-224 (2010) - [c71]Naotaka Maruyama, Tohru Ishihara, Hiroto Yasuura:
An RTOS in hardware for energy efficient software-based TCP/IP processing. SASP 2010: 58-63 - 2009
- [j26]Seiichiro Yamaguchi, Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura:
Single-Cycle-Accessible Two-Level Caches and Compilation Technique for Energy Reducion. IPSJ Trans. Syst. LSI Des. Methodol. 2: 189-199 (2009) - [j25]Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura:
An Optimization Technique for Low-Energy Embedded Memory Systems. IPSJ Trans. Syst. LSI Des. Methodol. 2: 239-249 (2009) - 2008
- [j23]Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura:
A software technique to improve lifetime of caches containing ultra-leaky SRAM cells caused by within-die Vth variation. Microelectron. J. 39(12): 1797-1808 (2008) - [c65]Tadayuki Matsumura, Tohru Ishihara, Hiroto Yasuura:
Simultaneous optimization of memory configuration and code allocation for low power embedded systems. ACM Great Lakes Symposium on VLSI 2008: 403-406 - [c63]Masanori Muroyama, Tohru Ishihara, Hiroto Yasuura:
Analysis of Effects of Input Arrival Time Variations on On-Chip Bus Power Consumption. PATMOS 2008: 62-71 - 2007
- [c61]Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura:
A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation. ASP-DAC 2007: 878-883 - [c60]Yuriko Ishitobi, Tohru Ishihara, Hiroto Yasuura:
Code Placement for Reducing the Energy Consumption of Embedded Processors with Scratchpad and Cache Memories. ESTIMedia 2007: 13-18 - 2006
- [c55]Donghoon Lee, Tohru Ishihara, Masanori Muroyama, Hiroto Yasuura, Farzan Fallah:
An Energy Characterization Framework for Software-Based Embedded Systems. ESTIMedia 2006: 59-64 - 2002
- [c36]Masanori Muroyama, Tohru Ishihara, Akihiko Hyodo, Hiroto Yasuura:
A Power Minimization Technique for Arithmetic Circuits by Cell Selection. ASP-DAC/VLSI Design 2002: 268-273 - 2001
- [j14]Takanori Okuma, Hiroto Yasuura, Tohru Ishihara:
Software Energy Reduction Techniques for Variable-Voltage Processors. IEEE Des. Test Comput. 18(2): 31-41 (2001) - 2000
- [j11]Akihiko Inoue, Tohru Ishihara, Hiroto Yasuura:
Flexible System LSI for Embedded Systems and Its Optimization Techniques. Des. Autom. Embed. Syst. 5(2): 179-205 (2000) - [c30]Tohru Ishihara, Hiroto Yasuura:
A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors. DATE 2000: 617-623 - 1999
- [c26]Takanori Okuma, Tohru Ishihara, Hiroto Yasuura:
Real-Time Task Scheduling for a Variable Voltage Processor. ISSS 1999: 24-29 - 1998
- [c24]Tohru Ishihara, Hiroto Yasuura:
Power-Pro: Programmable Power Management Architecture. ASP-DAC 1998: 321-322 - [c23]Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura:
Instruction Scheduling for Power Reduction in Processor-Based System Design. DATE 1998: 855-860 - [c22]Tohru Ishihara, Hiroto Yasuura:
Voltage scheduling problem for dynamically variable voltage processors. ISLPED 1998: 197-202 - 1996
- [c14]Tohru Ishihara, Hiroto Yasuura:
Basic experimentation on accuracy of power estimation for CMOS VLSI circuits. ISLPED 1996: 117-120
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