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Román Hermida
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Publications
- 2014
- [j27]Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik, Jose Manuel Mendias, María C. Molina:
Improving circuit performance with multispeculative additive trees in high-level synthesis. Microelectron. J. 45(11): 1470-1479 (2014) - 2013
- [j25]Alberto A. Del Barrio, Seda Ogrenci Memik, María C. Molina, José M. Mendías, Román Hermida:
A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths. Integr. 46(2): 119-130 (2013) - [c56]Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik, Jose Manuel Mendias, María C. Molina:
Multispeculative additive trees in high-level synthesis. DATE 2013: 188-193 - 2012
- [j23]Alberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik, José M. Mendías, María C. Molina:
Multispeculative Addition Applied to Datapath Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(12): 1817-1830 (2012) - 2011
- [j22]Alberto A. Del Barrio, Seda Ogrenci Memik, María C. Molina, Jose Manuel Mendias, Román Hermida:
A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(3): 350-363 (2011) - [c54]Alberto A. Del Barrio, Seda Ogrenci Memik, María C. Molina, José M. Mendías, Román Hermida:
Power optimization in heterogenous datapaths. DATE 2011: 1400-1405 - 2010
- [c53]Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Román Hermida, Seda Ogrenci Memik:
Using Speculative Functional Units in high level synthesis. DATE 2010: 1779-1784 - 2008
- [c52]Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Esther Andres Perez, Román Hermida:
Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis. DSD 2008: 267-273 - [c51]Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Esther Andres Perez, Román Hermida, Francisco Tirado:
Applying speculation techniques to implement functional units. ICCD 2008: 74-80 - 2007
- [j18]David Atienza, Pablo García Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida:
HW-SW emulation framework for temperature-aware design in MPSoCs. ACM Trans. Design Autom. Electr. Syst. 12(3): 26:1-26:26 (2007) - [c50]María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida:
Area optimization of multi-cycle operators in high-level synthesis. DATE 2007: 449-454 - [i1]Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida:
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis. CoRR abs/0710.4801 (2007) - 2006
- [j17]María C. Molina, Rafael Ruiz-Sautua, Jose Manuel Mendias, Román Hermida:
Bitwise scheduling to balance the computational cost of behavioral specifications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(1): 31-46 (2006) - [c49]Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida:
Pre-synthesis optimization of multiplications to improve circuit performance. DATE 2006: 1306-1311 - 2005
- [c47]Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida:
Arrival time aware scheduling to minimize clock cycle length. ASP-DAC 2005: 1018-1021 - [c46]Nicolas Genko, David Atienza, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida, Francky Catthoor:
A Complete Network-On-Chip Emulation Framework. DATE 2005: 246-251 - [c45]Rafael Ruiz-Sautua, María C. Molina, José M. Mendías, Román Hermida:
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis. DATE 2005: 1252-1257 - [c44]Rafael Ruiz-Sautua, María C. Molina, Jose Manuel Mendias, Román Hermida:
Performance-driven read-after-write dependencies softening in high-level synthesis. ICCAD 2005: 7-12 - [c42]Nicolas Genko, David Atienza, Giovanni De Micheli, Luca Benini, Jose Manuel Mendias, Román Hermida, Francky Catthoor:
A novel approach for network on chip emulation. ISCAS (3) 2005: 2365-2368 - [c41]J. B. Pérez-Ramas, David Atienza, Miguel Peón Quirós, Ivan Magan, Jose Manuel Mendias, Román Hermida:
Versatile FPGA-Based Functional Validation Framework for Networks-on-Chip Interconnections Designs. PARCO 2005: 769-776 - 2004
- [c39]María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida:
Behavioural Bitwise Scheduling Based on Computational Effort Balancing. DATE 2004: 684-685 - [c38]María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida:
Behavioural Scheduling to Balance the Bit-Level Computational Effort. ISVLSI 2004: 99-104 - 2003
- [j14]María C. Molina, José M. Mendías, Román Hermida:
Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources. J. Syst. Archit. 49(12-15): 505-519 (2003) - [c35]María C. Molina, José M. Mendías, Román Hermida:
High-Level Allocation to Minimize Internal Hardware Wastage. DATE 2003: 10264-10269 - [c32]María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida:
Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis. PATMOS 2003: 617-627 - 2002
- [j12]José M. Mendías, Román Hermida, Olga Peñalba:
A study about the efficiency of formal high-level synthesis applied to verification. Integr. 31(2): 101-131 (2002) - [j11]Olga Peñalba, José M. Mendías, Román Hermida:
A global approach to improve conditional hardware reuse in high-level synthesis. J. Syst. Archit. 47(12): 959-975 (2002) - [c31]María C. Molina, José M. Mendías, Román Hermida:
High-level synthesis of multiple-precision circuitsindependent of data-objects length. DAC 2002: 612-615 - [c28]María C. Molina, José M. Mendías, Román Hermida:
Multiple-Precision Circuits Allocation Independent of Data-Objects Length. DATE 2002: 909-913 - [c27]Olga Peñalba, José M. Mendías, Román Hermida:
Maximizing Conditonal Reuse by Pre-Synthesis Transformations. DATE 2002: 1097 - [c25]Aitor Ibarra, José M. Mendías, Juan Lanchares, José Ignacio Hidalgo, Román Hermida:
Optimization of Equational Specifications Using Genetic Techniques. DSD 2002: 252-258 - [c24]José M. Mendías, Román Hermida, María C. Molina, Olga Peñalba:
Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis. DSD 2002: 308-315 - [c23]Olga Peñalba, José M. Mendías, Román Hermida:
Source Code Transformation to Improve Conditional Hardware Reuse. DSD 2002: 324-331 - [c22]María C. Molina, José M. Mendías, Román Hermida:
Bit-Level Allocation of Multiple-Precision Specifications. DSD 2002: 385-392 - [c21]Aitor Ibarra, Juan Lanchares, Jose Manuel Mendias, José Ignacio Hidalgo, Román Hermida:
Transformation of Equational Specification by Means of Genetic Programming. EuroGP 2002: 248-257 - [c20]María C. Molina, José M. Mendías, Román Hermida:
Bit-level scheduling of heterogeneous behavioural specifications. ICCAD 2002: 602-608 - 1999
- [c9]Olga Peñalba, José M. Mendías, Román Hermida:
A Unified Algorithm for Mutual Exclusiveness Identification. EUROMICRO 1999: 1504-1510 - 1998
- [c6]José M. Mendías, Román Hermida:
Correct High-Level Synthesis: a Formal Perspective. DATE 1998: 977-978 - 1997
- [c4]José M. Mendías, Román Hermida, Milagros Fernández:
Formal Techniques for Hardware Allocation. VLSI Design 1997: 161-165 - 1996
- [c3]José M. Mendías, Román Hermida, Milagros Fernández:
Algebraic Support for Transformational Hardware Allocation. ED&TC 1996: 601
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