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Zhenxue He
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Publications
- 2023
- [j20]Yuhao Zhou, Zhenxue He, Yan Zhang, Jia Liu, Tao Wang, Limin Xiao, Xiang Wang:
Power Optimization for Mixed Polarity Reed-Muller Circuits Based on Multilevel Adaptive Memetic Algorithm. Int. J. Intell. Syst. 2023: 1-18 (2023) - [j19]Yuhao Zhou, Zhenxue He, Jianhui Jiang, Jia Liu, Juncai He, Tao Wang, Limin Xiao, Xiang Wang:
Fast Area Optimization Approach for XNOR/OR-based Fixed Polarity Reed-Muller Logic Circuits based on Multi-strategy Wolf Pack Algorithm. ACM Trans. Design Autom. Electr. Syst. 28(3): 45:1-45:16 (2023) - 2022
- [j18]Yuhao Zhou, Zhenxue He, Tao Wang, Zhisheng Huo, Limin Xiao, Xiang Wang:
Area and power optimization approach for mixed polarity Reed-Muller logic circuits based on multi-strategy bacterial foraging algorithm. Appl. Soft Comput. 130: 109720 (2022) - [j17]Yuhao Zhou, Zhenxue He, Chen Chen, Tao Wang, Limin Xiao, Xiang Wang:
An Efficient Power Optimization Approach for Fixed Polarity Reed-Muller Logic Circuits Based on Metaheuristic Optimization Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(12): 5380-5393 (2022) - 2021
- [j16]Zhenxue He, Yu-hua Pan, Ke-jian Wang, Limin Xiao, Xiang Wang:
Area optimization for MPRM logic circuits based on improved multiple disturbances fireworks algorithm. Appl. Math. Comput. 399: 126008 (2021) - [j15]Zhenxue He, Limin Xiao, Xiang Wang:
Minimization for ternary fixed polarity Reed-Muller expressions based on ternary quantum shuffled frog leaping algorithm. Appl. Soft Comput. 110: 107647 (2021) - [j14]Zhenxue He, Xiaoqian Wu, Chao Wang, Zhisheng Huo, Limin Xiao, Xiang Wang:
Delay optimization for ternary fixed polarity Reed-Muller circuits based on multilevel adaptive quantum genetic algorithm. Int. J. Intell. Syst. 36(10): 5981-6006 (2021) - 2020
- [j12]Tao Wang, Xiang Wang, Wei Shi, Zongmin Zhao, Zhenxue He, Tongsheng Xia:
Target localization and tracking based on improved Bayesian enhanced least-squares algorithm in wireless sensor networks. Comput. Networks 167 (2020) - 2019
- [j11]Zhenxue He, Limin Xiao, Zhisheng Huo, Tao Wang, Xiang Wang:
Fast Minimization of Fixed Polarity Reed-Muller Expressions. IEEE Access 7: 24843-24851 (2019) - [j10]Zhenxue He, Jia Liu, Limin Xiao, Zhisheng Huo, Xiang Wang:
A Polarity Optimization Algorithm Taking Into Account Polarity Conversion Sequence. IEEE Access 7: 54809-54818 (2019) - [j8]Zhenxue He, Limin Xiao, Fei Gu, Li Ruan, Zhisheng Huo, Mingzhe Li, Mingfa Zhu, Longbing Zhang, Rui Liu, Xiang Wang:
EDOA: an efficient delay optimization approach for mixed-polarity Reed-Muller logic circuits under the unit delay model. Frontiers Comput. Sci. 13(5): 1102-1115 (2019) - 2017
- [j4]Zhenxue He, Limin Xiao, Fei Gu, Tongsheng Xia, Shubin Su, Zhisheng Huo, Rong Zhang, Longbing Zhang, Li Ruan, Xiang Wang:
An efficient and fast polarity optimization approach for mixed polarity Reed-Muller logic circuits. Frontiers Comput. Sci. 11(4): 728-742 (2017) - [j3]Zhenxue He, Limin Xiao, Li Ruan, Fei Gu, Zhisheng Huo, Guangjun Qin, Mingfa Zhu, Longbing Zhang, Rui Liu, Xiang Wang:
A Power and Area Optimization Approach of Mixed Polarity Reed-Muller Expression for Incompletely Specified Boolean Functions. J. Comput. Sci. Technol. 32(2): 297-311 (2017) - [c8]Xiang Wang, Mingzhe Li, Zhenxue He, Weike Wang, Cheng Zhou, Zongmin Zhao:
PAOA: A power and area optimization approach of reed-muller logic circuits. MWSCAS 2017: 1394-1397 - [c7]Zhenxue He, Guangjun Qin, Limin Xiao, Fei Gu, Zhisheng Huo, Li Ruan, Haitao Wang, Longbing Zhang, Jianbin Liu, Shaobo Liu, Xiang Wang:
An Efficient Polarity Optimization Approach for Fixed Polarity Reed-Muller Logic Circuits Based on Novel Binary Differential Evolution Algorithm. NPC 2017: 118-121 - 2016
- [c6]Zhenxue He, Limin Xiao, Longbing Zhang, Fei Gu, Zhisheng Huo, Mingfa Zhu, Li Ruan, Rui Liu, Xiang Wang:
EMA-FPRMs: An efficient minimization algorithm for fixed polarity Reed-Muller expressions. FPT 2016: 253-256 - 2015
- [c3]Limin Xiao, Zhenxue He, Li Ruan, Rong Zhang, Tongsheng Xia, Xiang Wang:
Optimization of best polarity searching for mixed polarity reed-muller logic circuit. SoCC 2015: 275-280 - [c2]Xiang Wang, Rong Zhang, Weike Wang, Zhenxue He, Lin Li, Quanneng Shen, Li Ruan, Limin Xiao:
Polarity Searching for MPRM Logic Circuit Based on Improved Adaptive Genetic Algorithm. UIC/ATC/ScalCom 2015: 1354-1358 - [c1]Xiang Wang, Liping Wang, Yuanchen Bai, Zhenxue He, Tao Wang, Bin Xu, He Zhang, Xiaocui Wang, Cheng Zhou, Weike Wang, Pei Du:
Optimization of Elliptic Curve Cryptography Resisting Power Attack Scalar Multiplication Algorithm in Security System on Chip. UIC/ATC/ScalCom 2015: 1397-1401
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