Akhilesh Tyagi

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Swamy D. Ponpandi

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Publications

2017
[j19]
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  - journals/integration/VenkatesanPT17
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Varun Venkatesan, Swamy D. Ponpandi, Akhilesh Tyagi:
Shaping data for application performance and energy optimization in dynamic data view framework. Integr. 58: 311-319 (2017)
2015
[c59]
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  - conf/ises/VenkatesanPT15
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Varun Venkatesan, Swamy D. Ponpandi, Akhilesh Tyagi:
Dynamic Data Shapers Optimize Performance in Dynamic Binary Optimization (DBO) Environment. iNIS 2015: 325-330
2014
[j16]
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  - journals/cee/PonpandiT14
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Swamy D. Ponpandi, Akhilesh Tyagi:
User satisfaction aware routing and energy modeling of polymorphic network on chip architecture. Comput. Electr. Eng. 40(8): 260-275 (2014)
[j15]
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  - journals/ijes/KeungPT14
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Ka-Ming Keung, Swamy D. Ponpandi, Akhilesh Tyagi:
A placer for composable FPGA with 2D mesh network. Int. J. Embed. Syst. 6(4): 289-302 (2014)
[c58]
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  - conf/ipps/ZhangPT14
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Zhang Zhang, Swamy D. Ponpandi, Akhilesh Tyagi:
An Evaluation of User Satisfaction Driven Scheduling in a Polymorphic Embedded System. IPDPS Workshops 2014: 263-268
2013
[c54]
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  - conf/micro/PonpandiT13
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Swamy D. Ponpandi, Akhilesh Tyagi:
User satisfaction aware routing decisions in NOC. NoCArc@MICRO 2013: 11-16
[c53]
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  - conf/reconfig/PonpandiZT13
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Swamy D. Ponpandi, Zhang Zhang, Akhilesh Tyagi:
PolyNOC - A polymorphic thread simulator for NoC communication based embedded systems. ReConFig 2013: 1-8
2011
[c50]
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  - conf/cases/KrishnamurthyPT11
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Viswanath Krishnamurthy, Swamy D. Ponpandi, Akhilesh Tyagi:
A novel thread scheduler design for polymorphic embedded systems. CASES 2011: 75-84
[c48]
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  - conf/fpt/PonpandiT11
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Swamy D. Ponpandi, Akhilesh Tyagi:
Partial reconfiguration logic synthesis by temporal slicing. FPT 2011: 1-6

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