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Román Hermida

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Juan Lanchares

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Publications

2004
[j15]
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  - journals/todaes/VicenteLH04
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Juan de Vicente, Juan Lanchares, Román Hermida:
Annealing placement by thermodynamic combinatorial optimization. ACM Trans. Design Autom. Electr. Syst. 9(3): 310-332 (2004)
[c37]
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  - conf/pdp/ColmenarGLHLH04
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José Manuel Colmenar, Oscar Garnica, Sonia López, José Ignacio Hidalgo, Juan Lanchares, Román Hermida:
Empirical Characterization of the Latency of Long Asynchronous Pipelines with Data-Dependent Module Delays. PDP 2004: 112-119
2003
[c34]
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  - conf/gecco/HidalgoVLSHTBPG03
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  - https://dblp.org/rec/conf/gecco/HidalgoVLSHTBPG03
José Ignacio Hidalgo, Francisco Fernández, Juan Lanchares, Juan Manuel Sánchez-Pérez, Román Hermida, Marco Tomassini, Ranieri Baraglia, Raffaele Perego, Oscar Garnica:
Multi-FPGA Systems Synthesis by Means of Evolutionary Computation. GECCO 2003: 2109-2120
[c33]
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  - conf/patmos/LopezGHLH03
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Sonia López, Oscar Garnica, José Ignacio Hidalgo, Juan Lanchares, Román Hermida:
Power-Consumption RRRRreduction in Asynchronous Circuits Using Delay Path Unequalization. PATMOS 2003: 151-160
2002
[j13]
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  - electronic edition @ iospress.com
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  - journals/fuin/GarnicaLH02
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Oscar Garnica, Juan Lanchares, Román Hermida:
Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation. Fundam. Informaticae 50(2): 155-174 (2002)
[c30]
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  - conf/date/VicenteLH02
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Juan de Vicente, Juan Lanchares, Román Hermida:
FPGA Placement by Thermodynamic Combinatorial Optimization. DATE 2002: 54-60
[c26]
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  - conf/dsd/HidalgoLIH02
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José Ignacio Hidalgo, Juan Lanchares, Aitor Ibarra, Román Hermida:
A Hybrid Evolutionary Algorithm for Multi-FPGA Systems Design. DSD 2002: 60-69
[c25]
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  - conf/dsd/IbarraMLHH02
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Aitor Ibarra, José M. Mendías, Juan Lanchares, José Ignacio Hidalgo, Román Hermida:
Optimization of Equational Specifications Using Genetic Techniques. DSD 2002: 252-258
[c21]
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  - conf/eurogp/IbarraLMHH02
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Aitor Ibarra, Juan Lanchares, Jose Manuel Mendias, José Ignacio Hidalgo, Román Hermida:
Transformation of Equational Specification by Means of Genetic Programming. EuroGP 2002: 248-257
[c19]
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  - conf/patmos/GarnicaLH02
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Oscar Garnica, Juan Lanchares, Román Hermida:
A New Methodology to Design Low-Power Asynchronous Circuits. PATMOS 2002: 108-117
2001
[c18]
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  - conf/acsd/GarnicaLH01
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Oscar Garnica, Juan Lanchares, Román Hermida:
Optimization of Asynchronous Delay-Insensitive Pipeline Latency Using Stage Reorganization and Optimal Stage Parameter Estimation. ACSD 2001: 167-178
[c17]
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  - conf/date/GarnicaLH01
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Oscar Garnica, Juan Lanchares, Román Hermida:
A pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits. DATE 2001: 810
2000
[c15]
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  - conf/euromicro/HidalgoLH00
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José Ignacio Hidalgo, Juan Lanchares, Román Hermida:
Partitioning and Placement for Multi-FPGA Systems Using Genetic Algorithms. EUROMICRO 2000: 1204-1211
[c12]
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  - conf/rsp/VicenteLH00
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Juan de Vicente, Juan Lanchares, Román Hermida:
Adaptive FPGA Placement by Natural Optimization. IEEE International Workshop on Rapid System Prototyping 2000: 188-193
1999
[c8]
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  - conf/fpl/VicenteLH99
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Juan de Vicente, Juan Lanchares, Román Hermida:
Placement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies. FPL 1999: 91-100
1998
[c5]
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  - conf/euromicro/VicenteLH98
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Juan de Vicente, Juan Lanchares, Román Hermida:
RSR: A New Rectilinear Steiner Minimum Tree Approximation for FPGA Placement and Global Routing. EUROMICRO 1998: 10192-10195

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