Vivek Seshadri

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Saugata Ghose

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Publications

2020
[c23]
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Nastaran Hajinazar, Pratyush Patel, Minesh Patel, Konstantinos Kanellopoulos, Saugata Ghose, Rachata Ausavarungnirun, Geraldo F. Oliveira, Jonathan Appavoo, Vivek Seshadri, Onur Mutlu:
The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework. ISCA 2020: 1050-1063
[i17]
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  - journals/corr/abs-2005-09748
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Nastaran Hajinazar, Pratyush Patel, Minesh Patel, Konstantinos Kanellopoulos, Saugata Ghose, Rachata Ausavarungnirun, Geraldo F. Oliveira, Jonathan Appavoo, Vivek Seshadri, Onur Mutlu:
The Virtual Block Interface: A Flexible Alternative to the Conventional Virtual Memory Framework. CoRR abs/2005.09748 (2020)
2019
[i16]
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  - journals/corr/abs-1902-07344
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Lois Orosa, Yaohua Wang, Ivan Puddu, Mohammad Sadrosadati, Kaveh Razavi, Juan Gómez-Luna, Hasan Hassan, Nika Mansouri-Ghiasi, Arash Tavakkol, Minesh Patel, Jeremie S. Kim, Vivek Seshadri, Uksong Kang, Saugata Ghose, Rodolfo Azevedo, Onur Mutlu:
Dataplant: In-DRAM Security Mechanisms for Low-Cost Devices. CoRR abs/1902.07344 (2019)
2017
[j4]
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Donghyuk Lee, Samira Manabi Khan, Lavanya Subramanian, Saugata Ghose, Rachata Ausavarungnirun, Gennady Pekhimenko, Vivek Seshadri, Onur Mutlu:
Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms. Proc. ACM Meas. Anal. Comput. Syst. 1(1): 26:1-26:36 (2017)
[c15]
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Donghyuk Lee, Samira Manabi Khan, Lavanya Subramanian, Saugata Ghose, Rachata Ausavarungnirun, Gennady Pekhimenko, Vivek Seshadri, Onur Mutlu:
Design-Induced Latency Variation in Modern DRAM Chips: Characterization, Analysis, and Latency Reduction Mechanisms. SIGMETRICS (Abstracts) 2017: 54
2016
[i3]
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  - journals/corr/LeeKSAPSGM16
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Donghyuk Lee, Samira Manabi Khan, Lavanya Subramanian, Rachata Ausavarungnirun, Gennady Pekhimenko, Vivek Seshadri, Saugata Ghose, Onur Mutlu:
Reducing DRAM Latency by Exploiting Design-Induced Latency Variation in Modern DRAM Chips. CoRR abs/1610.09604 (2016)

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