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Stefan Cosemans
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Publications
- 2023
- [c35]Mohit Gupta, Stefan Cosemans, Peter Debacker, Wim Dehaene:
A 2Mbit Digital in-Memory Computing Matrix-Vector Multiplier for DNN Inference supporting flexible bit precision and matrix size achieving 612 binary TOPS/W. ESSCIRC 2023: 417-420 - 2018
- [j7]Innocent Agbo, Mottaqiallah Taouil, Daniel Kraak, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor, Wim Dehaene:
Impact and mitigation of SRAM read path aging. Microelectron. Reliab. 87: 158-167 (2018) - [c21]Jonas Doevenspeck, Robin Degraeve, Stefan Cosemans, Philippe Roussel, Bram-Ernst Verhoef, Rudy Lauwereins, Wim Dehaene:
Analytic variability study of inference accuracy in RRAM arrays with a binary tree winner-take-all circuit for neuromorphic applications. ESSDERC 2018: 62-65 - 2017
- [c19]Daniel Kraak, Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor, Wim Dehaene:
Mitigation of sense amplifier degradation using input switching. DATE 2017: 858-863 - [c18]Mohit Kumar Gupta, Pieter Weckx, Stefan Cosemans, Pieter Schuddinck, Rogier Baert, Dmitry Yakimets, Doyoung Jang, Yasser Sherazi, Praveen Raghavan, Alessio Spessot, Anda Mocuta, Wim Dehaene:
Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7. ESSDERC 2017: 256-259 - [c17]Mohit Kumar Gupta, Pieter Weckx, Stefan Cosemans, Pieter Schuddinck, Rogier Baert, Doyoung Jang, Yasser Sherazi, Praveen Raghavan, Alessio Spessot, Anda Mocuta, Wim Dehaene:
Dedicated technology threshold voltage tuning for 6T SRAM beyond N7. ICICDT 2017: 1-4 - 2016
- [c15]Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor, Wim Dehaene:
Read path degradation analysis in SRAM. ETS 2016: 1-2 - [c14]Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Praveen Raghavan, Francky Catthoor, Wim Dehaene:
Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability. ISVLSI 2016: 725-730 - 2015
- [c10]Raf Appeltans, Stefan Cosemans, Praveen Raghavan, Diederik Verkest, Liesbet Van der Perre, Wim Dehaene:
STT-MRAM cell design with partial source line planes: improving the trade-off between area and series resistance. NVMSA 2015: 1-6 - 2012
- [j5]Bram Rooseleer, Stefan Cosemans, Wim Dehaene:
A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, Ultra Low Leakage Power Memory Using Dynamic Cell Stability and a Dual Swing Data Link. IEEE J. Solid State Circuits 47(7): 1784-1796 (2012) - [j4]Vibhu Sharma, Stefan Cosemans, Maryam Ashouei, Jos Huisken, Francky Catthoor, Wim Dehaene:
Ultra Low-Energy SRAM Design for Smart Ubiquitous Sensors. IEEE Micro 32(5): 10-24 (2012) - [c9]Vibhu Sharma, Stefan Cosemans, Maryam Ashouei, Jos Huisken, Francky Catthoor, Wim Dehaene:
Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM. DATE 2012: 1042-1047 - 2011
- [j3]Vibhu Sharma, Stefan Cosemans, Maryam Ashouei, Jos Huisken, Francky Catthoor, Wim Dehaene:
A 4.4 pJ/Access 80 MHz, 128 kbit Variability Resilient SRAM With Multi-Sized Sense Amplifier Redundancy. IEEE J. Solid State Circuits 46(10): 2416-2430 (2011) - [c7]Bram Rooseleer, Stefan Cosemans, Wim Dehaene:
A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link. ESSCIRC 2011: 519-522 - [c6]Anselme Vignon, Stefan Cosemans, Wim Dehaene:
A low leakage 500MHz 2T embedded dynamic memory with integrated semi-transparent refresh. ESSCIRC 2011: 523-526 - [c5]Vibhu Sharma, Stefan Cosemans, Maryam Ashouei, Jos Huisken, Francky Catthoor, Wim Dehaene:
8T SRAM with Mimicked Negative Bit-lines and Charge Limited Sequential sense amplifier for wireless sensor nodes. ESSCIRC 2011: 531-534 - 2010
- [c4]Vibhu Sharma, Stefan Cosemans, Maryam Ashouei, Jos Huisken, Francky Catthoor, Wim Dehaene:
A 4.4pJ/access 80MHz, 2K word } 64b memory with write masking feature and variability resilient multi-sized sense amplifier redundancy for wireless sensor nodes applications. ESSCIRC 2010: 358-361 - 2009
- [j2]Stefan Cosemans, Wim Dehaene, Francky Catthoor:
A 3.6 pJ/Access 480 MHz, 128 kb On-Chip SRAM With 850 MHz Boost Mode in 90 nm CMOS With Tunable Sense Amplifiers. IEEE J. Solid State Circuits 44(7): 2065-2077 (2009) - [c3]Anselme Vignon, Stefan Cosemans, Wim Dehaene, Pol Marchal, Marco Facchini:
A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context. DATE 2009: 929-933 - 2008
- [c2]Stefan Cosemans, Wim Dehaene, Francky Catthoor:
A 3.6pJ/access 480MHz, 128Kbit on-Chip SRAM with 850MHz boost mode in 90nm CMOS with tunable sense amplifiers to cope with variability. ESSCIRC 2008: 278-281 - 2007
- [j1]Stefan Cosemans, Wim Dehaene, Francky Catthoor:
A Low-Power Embedded SRAM for Wireless Applications. IEEE J. Solid State Circuits 42(7): 1607-1617 (2007) - [c1]Wim Dehaene, Stefan Cosemans, Anselme Vignon, F. Catthoora, Peter Geens:
Embedded SRAM design in deep deep submicron technologies. ESSCIRC 2007: 384-391
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