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Jan Eitzinger
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Publications
- 2023
- [j12]Rafael Ravedutti Lucio Machado, Jan Eitzinger, Jan Laukemann, Georg Hager, Harald Köstler, Gerhard Wellein:
MD-Bench: A performance-focused prototyping harness for state-of-the-art short-range molecular dynamics algorithms. Future Gener. Comput. Syst. 149: 25-38 (2023) - [i25]Rafael Ravedutti Lucio Machado, Jan Eitzinger, Jan Laukemann, Georg Hager, Harald Köstler, Gerhard Wellein:
MD-Bench: Engineering the in-core performance of short-range molecular dynamics kernels from state-of-the-art simulation packages. CoRR abs/2302.14660 (2023) - 2017
- [j9]Johannes Hofmann, Dietmar Fey, Michael Riedmann, Jan Eitzinger, Georg Hager, Gerhard Wellein:
Performance analysis of the Kahan-enhanced scalar product on current multi-core and many-core processors. Concurr. Comput. Pract. Exp. 29(9) (2017) - [c18]Thomas Röhl, Jan Eitzinger, Georg Hager, Gerhard Wellein:
LIKWID Monitoring Stack: A Flexible Framework Enabling Job Specific Performance monitoring for the masses. CLUSTER 2017: 781-784 - [i22]Julian Hammer, Jan Eitzinger, Georg Hager, Gerhard Wellein:
Kerncraft: A Tool for Analytic Performance Modeling of Loop Kernels. CoRR abs/1702.04653 (2017) - [i21]Thomas Röhl, Jan Eitzinger, Georg Hager, Gerhard Wellein:
LIKWID Monitoring Stack: A flexible framework enabling job specific performance monitoring for the masses. CoRR abs/1708.01476 (2017) - [i20]Thomas Röhl, Jan Eitzinger, Georg Hager, Gerhard Wellein:
Validation of hardware events for successful performance pattern identification in High Performance Computing. CoRR abs/1710.04094 (2017) - 2016
- [j8]Georg Hager, Jan Treibig, Johannes Habich, Gerhard Wellein:
Exploring performance and power properties of modern multi-core chips via simple machine models. Concurr. Comput. Pract. Exp. 28(2): 189-210 (2016) - [j7]Markus Wittmann, Georg Hager, Thomas Zeiser, Jan Treibig, Gerhard Wellein:
Chip-level and multi-node analysis of energy-optimized lattice Boltzmann CFD simulations. Concurr. Comput. Pract. Exp. 28(7): 2295-2315 (2016) - [c17]Johannes Hofmann, Dietmar Fey, Jan Eitzinger, Georg Hager, Gerhard Wellein:
Analysis of Intel's Haswell Microarchitecture Using the ECM Model and Microbenchmarks. ARCS 2016: 210-222 - [i19]Johannes Hofmann, Dietmar Fey, Michael Riedmann, Jan Eitzinger, Georg Hager, Gerhard Wellein:
Performance analysis of the Kahan-enhanced scalar product on current multi- and manycore processors. CoRR abs/1604.01890 (2016) - 2015
- [c16]Holger Stengel, Jan Treibig, Georg Hager, Gerhard Wellein:
Quantifying Performance Bottlenecks of Stencil Computations Using the Execution-Cache-Memory Model. ICS 2015: 207-216 - [c15]Johannes Hofmann, Dietmar Fey, Michael Riedmann, Jan Eitzinger, Georg Hager, Gerhard Wellein:
Performance Analysis of the Kahan-Enhanced Scalar Product on Current Multicore Processors. PPAM (1) 2015: 63-73 - [c14]Julian Hammer, Georg Hager, Jan Eitzinger, Gerhard Wellein:
Automatic loop kernel analysis and performance modeling with Kerncraft. PMBS@SC 2015: 4:1-4:11 - [i18]Johannes Hofmann, Dietmar Fey, Jan Eitzinger, Georg Hager, Gerhard Wellein:
Performance analysis of the Kahan-enhanced scalar product on current multicore processors. CoRR abs/1505.02586 (2015) - [i16]Julian Hammer, Georg Hager, Jan Eitzinger, Gerhard Wellein:
Automatic Loop Kernel Analysis and Performance Modeling With Kerncraft. CoRR abs/1509.03778 (2015) - [i15]Johannes Hofmann, Dietmar Fey, Jan Eitzinger, Georg Hager, Gerhard Wellein:
Analysis of Intel's Haswell Microarchitecture Using The ECM Model and Microbenchmarks. CoRR abs/1511.03639 (2015) - 2014
- [c13]Johannes Hofmann, Jan Treibig, Georg Hager, Gerhard Wellein:
Performance Engineering for a Medical Imaging Application on the Intel Xeon Phi Accelerator. ARCS Workshops 2014: 1-8 - [c12]Thomas Roehl, Jan Treibig, Georg Hager, Gerhard Wellein:
Overhead Analysis of Performance Counter Measurements. ICPP Workshops 2014: 176-185 - [c11]Johannes Hofmann, Jan Treibig, Georg Hager, Gerhard Wellein:
Comparing the performance of different x86 SIMD instruction sets for a medical imaging application on modern multi- and manycore chips. WPMVP@PPoPP 2014: 57-64 - [i14]Johannes Hofmann, Jan Treibig, Georg Hager, Gerhard Wellein:
Performance Engineering for a Medical Imaging Application on the Intel Xeon Phi Accelerator. CoRR abs/1401.3615 (2014) - [i13]Johannes Hofmann, Jan Treibig, Georg Hager, Gerhard Wellein:
Comparing the Performance of Different x86 SIMD Instruction Sets for a Medical Imaging Application on Modern Multi- and Manycore Chips. CoRR abs/1401.7494 (2014) - [i12]Holger Stengel, Jan Treibig, Georg Hager, Gerhard Wellein:
Quantifying performance bottlenecks of stencil computations using the Execution-Cache-Memory model. CoRR abs/1410.5010 (2014) - 2013
- [j5]Jan Treibig, Georg Hager, Hannes G. Hofmann, Joachim Hornegger, Gerhard Wellein:
Pushing the limits for medical image reconstruction on recent standard multicore processors. Int. J. High Perform. Comput. Appl. 27(2): 162-177 (2013) - [i11]Christoph Scheit, Georg Hager, Jan Treibig, Stefan Becker, Gerhard Wellein:
Optimization of FASTEST-3D for Modern Multicore Systems. CoRR abs/1303.4538 (2013) - 2012
- [j4]Klaus Iglberger, Georg Hager, Jan Treibig, Ulrich Rüde:
Expression Templates Revisited: A Performance Analysis of Current Methodologies. SIAM J. Sci. Comput. 34(2) (2012) - [c8]Jan Treibig, Georg Hager, Gerhard Wellein:
Performance Patterns and Hardware Metrics on Modern Multicore Processors: Best Practices for Performance Engineering. Euro-Par Workshops 2012: 451-460 - [c7]Klaus Iglberger, Georg Hager, Jan Treibig, Ulrich Rüde:
High performance smart expression template math libraries. HPCS 2012: 367-373 - [i10]Jan Treibig, Georg Hager, Gerhard Wellein:
Best practices for HPM-assisted performance engineering on modern multicore processors. CoRR abs/1206.3738 (2012) - [i9]Georg Hager, Jan Treibig, Johannes Habich, Gerhard Wellein:
Exploring performance and power properties of modern multicore chips via simple machine models. CoRR abs/1208.2908 (2012) - 2011
- [j3]Jan Treibig, Gerhard Wellein, Georg Hager:
Efficient multicore-aware parallelization strategies for iterative stencil computations. J. Comput. Sci. 2(2): 130-137 (2011) - [c6]Jan Treibig, Georg Hager, Gerhard Wellein:
likwid-bench: An Extensible Microbenchmarking Platform for x86 Multicore Compute Nodes. Parallel Tools Workshop 2011: 27-36 - [c5]Jan Treibig, Georg Hager, Gerhard Wellein, Michael Meier:
Poster: LIKWID: lightweight performance tools. SC Companion 2011: 29-30 - [i8]Klaus Iglberger, Georg Hager, Jan Treibig, Ulrich Rüde:
Expression Templates Revisited: A Performance Analysis of the Current ET Methodology. CoRR abs/1104.1729 (2011) - [i7]Jan Treibig, Georg Hager, Gerhard Wellein:
LIKWID: Lightweight Performance Tools. CoRR abs/1104.4874 (2011) - [i6]Jan Treibig, Georg Hager, Hannes G. Hofmann, Joachim Hornegger, Gerhard Wellein:
Pushing the limits for medical image reconstruction on recent standard multicore processors. CoRR abs/1104.5243 (2011) - 2010
- [j2]Markus Wittmann, Georg Hager, Jan Treibig, Gerhard Wellein:
Leveraging Shared Caches for Parallel Temporal Blocking of Stencil Codes on Multicore Processors and Clusters. Parallel Process. Lett. 20(4): 359-376 (2010) - [c4]Jan Treibig, Georg Hager, Gerhard Wellein:
LIKWID: Lightweight Performance Tools. CHPC 2010: 165-175 - [c3]Jan Treibig, Georg Hager, Gerhard Wellein:
LIKWID: A Lightweight Performance-Oriented Tool Suite for x86 Multicore Environments. ICPP Workshops 2010: 207-216 - [i5]Jan Treibig, Gerhard Wellein, Georg Hager:
Efficient multicore-aware parallelization strategies for iterative stencil computations. CoRR abs/1004.1741 (2010) - [i4]Jan Treibig, Georg Hager, Gerhard Wellein:
LIKWID: A lightweight performance-oriented tool suite for x86 multicore environments. CoRR abs/1004.4431 (2010) - [i3]Markus Wittmann, Georg Hager, Jan Treibig, Gerhard Wellein:
Leveraging shared caches for parallel temporal blocking of stencil codes on multicore processors and clusters. CoRR abs/1006.3148 (2010) - 2009
- [c2]Jan Treibig, Georg Hager:
Introducing a Performance Model for Bandwidth-Limited Loop Kernels. PPAM (1) 2009: 615-624 - [i2]Jan Treibig, Georg Hager:
Introducing a Performance Model for Bandwidth-Limited Loop Kernels. CoRR abs/0905.0792 (2009) - [i1]Jan Treibig, Georg Hager, Gerhard Wellein:
Multi-core architectures: Complexities of performance prediction and the impact of cache topology. CoRR abs/0910.4865 (2009)
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