Alan J. Drake

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Michael S. Floyd

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Publications

2013
[j6]
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Michael S. Floyd, Alan J. Drake, Nicole S. Schwartz, Robert W. Berry, Charles Lefurgy, Malcolm S. Ware, Karthick Rajamani, Victor V. Zyuban, Richard L. Willaman, Ruby M. Zgabay:
Runtime power reduction capability of the IBM POWER7+ chip. IBM J. Res. Dev. 57(6) (2013)
[j5]
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Charles Lefurgy, Alan J. Drake, Michael S. Floyd, Malcolm Allen-Ware, Bishop Brock, José A. Tierno, John B. Carter, Robert W. Berry:
Active Guardband Management in Power7+ to Save Energy and Maintain Reliability. IEEE Micro 33(4): 35-45 (2013)
[c10]
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Alan J. Drake, Michael S. Floyd, Richard L. Willaman, Derek J. Hathaway, Joshua Hernandez, Crystal Soja, Marshall D. Tiner, Gary D. Carpenter, Robert M. Senger:
Single-cycle, pulse-shaped critical path monitor in the POWER7+ microprocessor. ISLPED 2013: 193-198
2012
[c8]
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  - conf/vlsic/FloydDBCWP12
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Michael S. Floyd, Alan J. Drake, Robert W. Berry, Harold Chase, Richard L. Willaman, Jarom Peña:
Voltage droop reduction using throttling controlled by timing margin feedback. VLSIC 2012: 96-97
2011
[j4]
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  - journals/micro/FloydARBLDPGTBB11
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Michael S. Floyd, Malcolm Allen-Ware, Karthick Rajamani, Bishop Brock, Charles Lefurgy, Alan J. Drake, Lorena Pesantez, Tilman Gloekler, José A. Tierno, Pradip Bose, Alper Buyuktosunoglu:
Introducing the Adaptive Energy Management Features of the Power7 Chip. IEEE Micro 31(2): 60-75 (2011)
[c7]
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Charles Lefurgy, Alan J. Drake, Michael S. Floyd, Malcolm Allen-Ware, Bishop Brock, José A. Tierno, John B. Carter:
Active management of timing guardband to save energy in POWER7. MICRO 2011: 1-11
2010
[c6]
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  - conf/hotchips/FloydBWRDLP10
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Michael S. Floyd, Bishop Brock, Malcolm S. Ware, Karthick Rajamani, Alan J. Drake, Charles Lefurgy, Lorena Pesantez:
Adaptive energy management features of the POWER7TM processor. Hot Chips Symposium 2010: 1-18
2007
[c5]
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  - conf/isscc/JrakeSDCGNJFP07
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Alan J. Drake, Robert M. Senger, Harmander Deogun, Gary D. Carpenter, Soraya Ghiasi, Tuyet Nguyen, Norman K. James, Michael S. Floyd, Vikas Pokala:
A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor. ISSCC 2007: 398-399

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