Heechul Yun

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Farzad Farshchi

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Publications

2020
[c24]
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Farzad Farshchi, Qijing Huang, Heechul Yun:
BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors. RTAS 2020: 364-375
2019
[c22]
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  - conf/dac/FustosFY19
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Jacob Fustos, Farzad Farshchi, Heechul Yun:
SpectreGuard: An Efficient Data-centric Defense Mechanism against Spectre Attacks. DAC 2019: 61
[c20]
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Farzad Farshchi, Qijing Huang, Heechul Yun:
Integrating NVIDIA Deep Learning Accelerator (NVDLA) with RISC-V SoC on FireSim. EMC2@HPCA/CVPR/ISCA 2019: 21-25
[i9]
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  - journals/corr/abs-1903-06495
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Farzad Farshchi, Qijing Huang, Heechul Yun:
Integrating NVIDIA Deep Learning Accelerator (NVDLA) with RISC-V SoC on FireSim. CoRR abs/1903.06495 (2019)
2018
[c17]
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Farzad Farshchi, Prathap Kumar Valsan, Renato Mancuso, Heechul Yun:
Deterministic Memory Abstraction and Supporting Multicore System Architecture. ECRTS 2018: 1:1-1:25
2017
[j7]
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Prathap Kumar Valsan, Heechul Yun, Farzad Farshchi:
Addressing isolation challenges of non-blocking caches for multicore real-time systems. Real Time Syst. 53(5): 673-708 (2017)
[i7]
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Farzad Farshchi, Prathap Kumar Valsan, Renato Mancuso, Heechul Yun:
Deterministic Memory Abstraction and Supporting Cache Architecture for Real-Time Systems. CoRR abs/1707.05260 (2017)
2016
[c12]
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  - conf/rtas/ValsanYF16
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Prathap Kumar Valsan, Heechul Yun, Farzad Farshchi:
Taming Non-Blocking Caches to Improve Isolation in Multicore Real-Time Systems. RTAS 2016: 161-172

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