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Larysa Titarenko

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Kamil Mielcarek

> Home > Persons > Larysa Titarenko

Publications

2024
[j14]
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  - journals/access/BarkalovTMM24
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Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Malgorzata Mazurkiewicz:
Hardware Reduction for FSMs With Extended State Codes. IEEE Access 12: 42369-42384 (2024)
2022
[b5]
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  - series/lnee/BarkalovTMMK22
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Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Malgorzata Mazurkiewicz, Elzbieta Kawecka:
Logic Synthesis for VLSI-Based Combined Finite State Machines - Synthesis Targeting ASICs, CPLDs and FPGAs. Lecture Notes in Electrical Engineering 922, Springer 2022, ISBN 978-3-031-16026-4, pp. 1-286
[j13]
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  - journals/access/BarkalovTCM22
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Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski, Kamil Mielcarek:
Improving Characteristics of FSMs With Mixed Codes of Outputs. IEEE Access 10: 36152-36165 (2022)
[j11]
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  - journals/tcad/BarkalovTM22
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Alexander A. Barkalov, Larysa Titarenko, Kamil Mielcarek:
Reducing LUT Count for Mealy FSMs With Transformation of States. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(5): 1400-1411 (2022)
2020
[b4]
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  - series/lnee/BarkalovTMC20
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Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Slawomir Chmielewski:
Logic Synthesis for FPGA-Based Control Units - Structural Decomposition in Logic Design. Lecture Notes in Electrical Engineering 636, Springer 2020, ISBN 978-3-030-38294-0, pp. 1-241
[j9]
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  - journals/amcs/0001TM20
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Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek:
Improving characteristics of LUT-based Mealy FSMs. Int. J. Appl. Math. Comput. Sci. 30(4): 745-759 (2020)
2019
[c32]
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  - conf/mixdes/BarkalovTMKZ19
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Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Kazimierz Krzywicki, Wojciech Zajac:
Decreasing Number of LUTs for Moore FSMs. MIXDES 2019: 200-205
[c31]
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Alexander Barkalov, Larysa Titarenko, Slawomir Chmielewski, Kamil Mielcarek:
Design of FPGA-Based Mealy FSMs with Counters. MOCAST 2019: 1-4
[c30]
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Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek:
Designing FPGA-Based Mealy FSMs with Two Levels of Logic. MOCAST 2019: 1-4
[c29]
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Alexander Barkalov, Larysa Titarenko, Malgorzata Mazurkiewicz, Kamil Mielcarek:
Encoding of Microoperations in FPGA-Based Moore FSMs. MOCAST 2019: 1-4
2018
[j7]
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  - journals/amcs/BarkalovTM18
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Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek:
Hardware Reduction for Lut-Based Mealy FSMs. Int. J. Appl. Math. Comput. Sci. 28(3): 595-607 (2018)
[c28]
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Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Slawomir Chmielewski:
Design of FPGA-based Mealy FSMs with Counters. MIXDES 2018: 136-139
[c27]
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Alexander Barkalov, Larysa Titarenko, Malgorzata Mazurkiewicz, Kamil Mielcarek:
Encoding of Terms in LUT-based Mealy FSMs. MIXDES 2018: 145-148
[c26]
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Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek:
Twofold State Assignment for LUT-based Mealy FSMs. MIXDES 2018: 204-208
[c24]
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Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek:
Twofold state assignment for FPGA-based mealy FSMs. MOCAST 2018: 1-4
2017
[c23]
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  - conf/cisim/MielcarekBT17
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Kamil Mielcarek, Alexander Barkalov, Larisa Titarenko:
Designing Moore FSM with Transformation of State Codes. CISIM 2017: 557-568
[c22]
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Kamil Mielcarek, Alexander Barkalov, Larysa Titarenko:
Designing HFPGA-based Mealy FSMs with transformation of output functions. MIXDES 2017: 250-253
[c18]
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Kamil Mielcarek, Alexander Barkalov, Larysa Titarenko:
Designing Moore FSM with extended class codes. MOCAST 2017: 1-4

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