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Anna Bernasconi 0001
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Publications
- 2023
- [j37]Anna Bernasconi, Alessandro Berti, Valentina Ciriani, Gianna M. Del Corso, Innocenzo Fulginiti:
XOR-AND-XOR Logic Forms for Autosymmetric Functions and Applications to Quantum Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(6): 1861-1872 (2023) - 2022
- [j36]Anna Bernasconi, Valentina Ciriani, Tiziano Villa:
Exploiting Symmetrization and D-Reducibility for Approximate Logic Synthesis. IEEE Trans. Computers 71(1): 121-133 (2022) - [j35]Anna Bernasconi, Stelvio Cimato, Valentina Ciriani, Maria Chiara Molteni:
Multiplicative Complexity of XOR Based Regular Functions. IEEE Trans. Computers 71(11): 2927-2939 (2022) - [c52]Anna Bernasconi, Valentina Ciriani, Marco Longhi:
On the Optimal OBDD Representation of 2-XOR Boolean Affine Spaces. DATE 2022: 1437-1442 - 2021
- [c48]Anna Bernasconi, Valentina Ciriani:
Autosymmetry of Incompletely Specified Functions. DATE 2021: 360-365 - [c47]Padmanabhan Balasubramanian, Anna Bernasconi, Valentina Ciriani, Tiziano Villa:
A Boolean Heuristic for Disjoint SOP Synthesis. DSD 2021: 62-68 - 2020
- [j32]Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, Elena I. Vatajelu:
Stuck-At Fault Mitigation of Emerging Technologies Based Switching Lattices. J. Electron. Test. 36(3): 313-326 (2020) - [c46]Anna Bernasconi, Stelvio Cimato, Valentina Ciriani, Maria Chiara Molteni:
Multiplicative Complexity of Autosymmetric Functions: Theory and Applications to Security. DAC 2020: 1-6 - [c45]Anna Bernasconi, Valentina Ciriani, Jordi Cortadella, Tiziano Villa:
Computing the full quotient in bi-decomposition by approximation. DATE 2020: 580-585 - 2019
- [j31]Anna Bernasconi, Valentina Ciriani, Gabriella Trucco, Tiziano Villa:
Boolean Minimization of Projected Sums of Products via Boolean Relations. IEEE Trans. Computers 68(9): 1269-1282 (2019) - [c44]Anna Bernasconi, Valentina Ciriani, Tiziano Villa:
Approximate Logic Synthesis by Symmetrization. DATE 2019: 1655-1660 - [c43]Anna Bernasconi, Valentina Ciriani, Luca Frontini:
Testability of Switching Lattices in the Cellular Fault Model. DSD 2019: 320-327 - [c42]Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco, Elena I. Vatajelu:
Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model. LATS 2019: 1-6 - 2018
- [j30]Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, Tiziano Villa:
Enhancing logic synthesis of switching lattices by generalized Shannon decomposition methods. Microprocess. Microsystems 56: 193-203 (2018) - [j29]Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco:
Composition of switching lattices for regular and for decomposed functions. Microprocess. Microsystems 60: 207-218 (2018) - [c38]Anna Bernasconi, Valentina Ciriani, Luca Frontini:
Testability of Switching Lattices in the Stuck at Fault Model. VLSI-SoC 2018: 213-218 - 2017
- [j28]Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Mehdi Baradaran Tahoori:
Logic synthesis and testing techniques for switching nano-crossbar arrays. Microprocess. Microsystems 54: 14-25 (2017) - [c37]Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco:
Composition of Switching Lattices and Autosymmetric Boolean Function Synthesis. DSD 2017: 137-144 - 2016
- [j27]Anna Bernasconi, Valentina Ciriani:
Index-Resilient Zero-Suppressed BDDs: Definition and Operations. ACM Trans. Design Autom. Electr. Syst. 21(4): 72:1-72:27 (2016) - [c36]Dan Alexandrescu, Mustafa Altun, Lorena Anghel, Anna Bernasconi, Valentina Ciriani, Luca Frontini, Mehdi Baradaran Tahoori:
Synthesis and Performance Optimization of a Switching Nano-Crossbar Computer. DSD 2016: 334-341 - [c35]Anna Bernasconi, Valentina Ciriani, Luca Frontini, Valentino Liberali, Gabriella Trucco, Tiziano Villa:
Logic Synthesis for Switching Lattices by Decomposition with P-Circuits. DSD 2016: 423-430 - [c34]Anna Bernasconi, Valentina Ciriani, Luca Frontini, Gabriella Trucco:
Synthesis on switching lattices of Dimension-reducible Boolean functions. VLSI-SoC 2016: 1-6 - 2015
- [j26]Anna Bernasconi, Valentina Ciriani, Gabriella Trucco, Tiziano Villa:
Using Flexibility in P-Circuits by Boolean Relations. IEEE Trans. Computers 64(12): 3605-3618 (2015) - [j25]Anna Bernasconi, Valentina Ciriani, Lorenzo Lago:
On the error resilience of ordered binary decision diagrams. Theor. Comput. Sci. 595: 11-33 (2015) - [c33]Anna Bernasconi, Robert K. Brayton, Valentina Ciriani, Gabriella Trucco, Tiziano Villa:
Bi-Decomposition Using Boolean Relations. DSD 2015: 72-78 - [c32]Anna Bernasconi, Valentina Ciriani, Gabriella Trucco:
Biconditional-BDD Ordering for Autosymmetric Functions. DSD 2015: 211-217 - 2014
- [j24]Anna Bernasconi, Valentina Ciriani:
Autosymmetric and Dimension Reducible Multiple-Valued Functions. J. Multiple Valued Log. Soft Comput. 23(3-4): 265-292 (2014) - [c31]Anna Bernasconi, Valentina Ciriani:
2-SPP Approximate Synthesis for Error Tolerant Applications. DSD 2014: 411-418 - [c30]Anna Bernasconi, Valentina Ciriani:
Zero-Suppressed Binary Decision Diagrams Resilient to Index Faults. IFIP TCS 2014: 1-12 - [i4]Anna Bernasconi, Valentina Ciriani, Lorenzo Lago:
On the Error Resilience of Ordered Binary Decision Diagrams. CoRR abs/1404.3919 (2014) - 2013
- [j23]Anna Bernasconi, Valentina Ciriani, Gabriella Trucco, Tiziano Villa:
SOP restructuring by exploiting don't cares. Microprocess. Microsystems 37(8-A): 836-847 (2013) - [j22]Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli:
Compact DSOP and Partial DSOP Forms. Theory Comput. Syst. 53(4): 583-608 (2013) - [c29]Anna Bernasconi, Valentina Ciriani, Gabriella Trucco, Tiziano Villa:
Minimization of P-circuits using Boolean relations. DATE 2013: 996-1001 - [c28]Anna Bernasconi, Valentina Ciriani, Lorenzo Lago:
Error resilient OBDDs. DDECS 2013: 246-249 - [c27]Anna Bernasconi, Valentina Ciriani, Gabriella Trucco, Tiziano Villa:
Minimization of EP-SOPs via Boolean relations. VLSI-SoC 2013: 112-117 - 2012
- [j21]Anna Bernasconi, Valentina Ciriani, Valentino Liberali, Gabriella Trucco, Tiziano Villa:
Synthesis of P-circuits for logic restructuring. Integr. 45(3): 282-293 (2012) - [c26]Anna Bernasconi, Valentina Ciriani, Gabriella Trucco, Tiziano Villa:
Projected Don't Cares. DSD 2012: 57-64 - [i3]Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli:
Compact DSOP and partial DSOP Forms. CoRR abs/1204.5306 (2012) - 2011
- [j20]Anna Bernasconi, Valentina Ciriani:
Dimension-reducible Boolean functions based on affine spaces. ACM Trans. Design Autom. Electr. Syst. 16(2): 13:1-13:21 (2011) - [c25]Anna Bernasconi, Valentina Ciriani:
Compact and Testable Circuits for Regular Functions. ARCS Workshops 2011 - [c24]Anna Bernasconi, Valentina Ciriani, Valentino Liberali, Gabriella Trucco, Tiziano Villa:
An approximation algorithm for cofactoring-based synthesis. ACM Great Lakes Symposium on VLSI 2011: 193-198 - [c23]Anna Bernasconi, Valentina Ciriani:
Autosymmetric Multiple-Valued Functions: Theory and Spectral Characterization. ISMVL 2011: 10-15 - 2010
- [c22]Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli:
Fun at a Department Store: Data Mining Meets Switching Theory. FUN 2010: 41-52 - [c21]Anna Bernasconi, Valentina Ciriani:
Logic synthesis and testability of D-reducible functions. VLSI-SoC 2010: 280-285 - 2009
- [c20]Anna Bernasconi, Valentina Ciriani, Gabriella Trucco, Tiziano Villa:
On decomposing Boolean functions via extended cofactoring. DATE 2009: 1464-1469 - [c19]Anna Bernasconi, Valentina Ciriani, Gabriella Trucco, Tiziano Villa:
Logic Minimization and Testability of 2SPP-P-Circuits. DSD 2009: 773-780 - 2008
- [j19]Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler:
On the construction of small fully testable circuits with low depth. Microprocess. Microsystems 32(5-6): 263-269 (2008) - [j18]Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli:
Synthesis of Autosymmetric Functions in a New Three-Level Form. Theory Comput. Syst. 42(4): 450-464 (2008) - [j17]Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa:
Logic Minimization and Testability of 2-SPP Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(7): 1190-1202 (2008) - [j16]Anna Bernasconi, Valentina Ciriani, Roberto Cordone:
The optimization of kEP-SOPs: Computational complexity, approximability and experiments. ACM Trans. Design Autom. Electr. Syst. 13(2): 35:1-35:31 (2008) - [c18]Anna Bernasconi, Valentina Ciriani, Roberto Cordone:
On Projecting Sums of Products. DSD 2008: 787-794 - 2007
- [c17]Görschwin Fey, Anna Bernasconi, Valentina Ciriani, Rolf Drechsler:
On the Construction of Small Fully Testable Circuits with Low Depth. DSD 2007: 563-569 - [c15]Anna Bernasconi, Valentina Ciriani, Roberto Cordone:
An approximation algorithm for fully testable kEP-SOP networks. ACM Great Lakes Symposium on VLSI 2007: 417-422 - 2006
- [j15]Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli:
Exploiting Regularities for Boolean Function Synthesis. Theory Comput. Syst. 39(4): 485-501 (2006) - [j14]Valentina Ciriani, Anna Bernasconi, Rolf Drechsler:
Testability of SPP Three-Level Logic Networks in Static Fault Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2241-2248 (2006) - [c14]Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa:
Efficient minimization of fully testable 2-SPP networks. DATE 2006: 1300-1305 - [c13]Anna Bernasconi, Valentina Ciriani:
DRedSOP: Synthesis of a New Class of Regular Functions. DSD 2006: 377-384 - [c12]Anna Bernasconi, Valentina Ciriani, Roberto Cordone:
Logic Synthesis of EXOR Projected Sum of Products. VLSI-SoC (Selected Papers) 2006: 241-257 - [c11]Anna Bernasconi, Valentina Ciriani, Roberto Cordone:
EXOR Projected Sum of Products. VLSI-SoC 2006: 284-289 - 2004
- [j13]Valentina Ciriani, Nadia Pisanti, Anna Bernasconi:
Room allocation: a polynomial subcase of the quadratic assignment problem. Discret. Appl. Math. 144(3): 263-269 (2004) - 2003
- [j10]Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli:
Three-level logic minimization based on function regularities. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(8): 1005-1016 (2003) - [c10]Valentina Ciriani, Anna Bernasconi, Rolf Drechsler:
Stuck-At-Fault Testability of SPP Three-Level Logic Forms. VLSI-SoC (Selected Papers) 2003: 299-313 - [c9]Valentina Ciriani, Anna Bernasconi, Rolf Drechsler:
Testability of SPP Three-Level Logic Networks. VLSI-SOC 2003: 331-336 - 2002
- [c8]Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli:
Fast three-level logic minimization based on autosymmetry. DAC 2002: 425-430 - [c7]Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli:
Implicit Test of Regularity for Not Completely Specified Boolean Functions. IWLS 2002: 345-350
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last updated on 2023-12-10 01:38 CET by the dblp team
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