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ORCIDMinkyu Je
Publications
- 2024
[c100]Sohyeon Kim, Injun Choi, Minkyu Je, Ji-Hoon Kim:
Dynamic Resource Management in Reconfigurable SoC for Multi-Tenancy Support. ISCAS 2024: 1-5- [c95]Sunyoung Park, Wooseok Byun, Minkyu Je, Ji-Hoon Kim:
Algorithm-Hardware Co-Design for Wearable BCIs: An Evolution from Linear Algebra to Transformers. ISCAS 2024: 1-5 - 2022
- [j54]Arup K. George
, Wooyoon Shim, Jaeha Kung, Ji-Hoon Kim, Minkyu Je, Junghyup Lee:
A 46-nF/10-MΩ Range 114-aF/0.37-Ω Resolution Parasitic- and Temperature-Insensitive Reconfigurable RC-to-Digital Converter in 0.18-μm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 69(3): 1171-1184 (2022) - [j53]Wooseok Byun, Minkyu Je, Ji-Hoon Kim:
An Energy-Efficient Domain-Specific Reconfigurable Array Processor With Heterogeneous PEs for Wearable Brain-Computer Interface SoCs. IEEE Trans. Circuits Syst. I Regul. Pap. 69(12): 4872-4885 (2022) - [j52]Wooseok Byun, Minkyu Je, Ji-Hoon Kim:
Advances in Wearable Brain-Computer Interfaces From an Algorithm-Hardware Co-Design Perspective. IEEE Trans. Circuits Syst. II Express Briefs 69(7): 3071-3077 (2022) - 2021
- [c70]Sujin Kim, Hoyong Sung, Sohyeon Kim, Minkyu Je, Ji-Hoon Kim:
ML-Based Humidity and Temperature Calibration System for Heterogeneous MOx Sensor Array in ppm-Level BTEX Monitoring. ISCAS 2021: 1-5 - [c64]Wooseok Byun, Minkyu Je, Ji-Hoon Kim:
A 2144.2-bits/min/mW 5-Heterogeneous PE-based Domain-Specific Reconfigurable Array Processor for 8-Ch Wearable Brain-Computer Interface SoC. VLSI Circuits 2021: 1-2 - 2019
- [c52]Taeju Lee, Jee-Ho Park, Ji-Hyoung Cha, Namsun Chou, Doojin Jang, Ji-Hoon Kim, Il-Joo Cho, Seong-Jin Kim, Minkyu Je:
A Multimodal Multichannel Neural Activity Readout IC with 0.7μW/Channel Ca2+-Probe-Based Fluorescence Recording and Electrical Recording. VLSI Circuits 2019: 290- - 2018
- [c45]Sehwan Lee, Arup K. George, Taeju Lee, Jun-Uk Chu, Sungmin Han, Ji-Hoon Kim, Minkyu Je, Junghyup Lee:
A 110dB-CMRR 100dB-PSRR multi-channel neural-recording amplifier system using differentially regulated rejection ratio enhancement in 0.18μm CMOS. ISSCC 2018: 472-474
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last updated on 2024-09-19 00:34 CEST by the dblp team
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