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Jiun-In Guo

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Chien-Chang Lin

> Home > Persons > Jiun-In Guo

Publications

2007
[j14]
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  - journals/jssc/LinCCYOTGW07
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  - https://dblp.org/rec/journals/jssc/LinCCYOTGW07
Chien-Chang Lin, Jia-Wei Chen, Hsiu-Cheng Chang, Yao-Chang Yang, Yi-Huan Ou-Yang, Ming-Chih Tsai, Jiun-In Guo, Jinn-Shyan Wang:
A 160K Gates/4.5 KB SRAM H.264 Video Decoder for HDTV Applications. IEEE J. Solid State Circuits 42(1): 170-182 (2007)
[c39]
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  dblp key:
  - conf/isscc/ChangCSYLCCYLCWG07
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  - https://dblp.org/rec/conf/isscc/ChangCSYLCCYLCWG07
Hsiu-Cheng Chang, Jia-Wei Chen, Ching-Lung Su, Yao-Chang Yang, Yao Li, Chun-Hao Chang, Ze-Min Chen, Wei-Sen Yang, Chien-Chang Lin, Ching-Wen Chen, Jinn-Shyan Wang, Jiun-In Guo:
A 7mW-to-183mW Dynamic Quality-Scalable H.264 Video Encoder Chip. ISSCC 2007: 280-603
[c38]
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  - conf/isscc/ChienLSCHYCCG07
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Chih-Da Chien, Chien-Chang Lin, Yi-Hung Shih, He-Chun Chen, Chia-Jui Huang, Cheng-Yen Yu, Chih-Liang Chen, Ching-Hwa Cheng, Jiun-In Guo:
A 252kgate/71mW Multi-Standard Multi-Channel Video Decoder for High Definition Video Applications. ISSCC 2007: 282-603
2006
[c33]
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  - conf/icassp/ChenLGW06
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  - https://dblp.org/rec/conf/icassp/ChenLGW06
Jia-Wei Chen, Chien-Chang Lin, Jiun-In Guo, Jinn-Shyan Wang:
Low Complexity Architecture Design of H.264 Predictive Pixel Compensator for HDTV Application. ICASSP (3) 2006: 932-935
[c31]
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  dblp key:
  - conf/icmcs/YangLCSG06
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  - https://dblp.org/rec/conf/icmcs/YangLCSG06
Yao-Chang Yang, Chien-Chang Lin, Hsui-Cheng Chang, Ching-Lung Su, Jiun-In Guo:
A High Throughput VLSI Architecture Design for H.264 Context-Based Adaptive Binary Arithmetic Decoding with Look Ahead Parsing. ICME 2006: 357-360
[c30]
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Jia-Wei Chen, Chun-Hao Chang, Chien-Chang Lin, Yi-Huan Yang, Jiun-In Guo, Jinn-Shyan Wang:
A Condition-based Intra Prediction Algorithm for H.264/AVC. ICME 2006: 1077-1080
2005
[c23]
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  - conf/iscas/ChangLG05
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Hsiu-Cheng Chang, Chien-Chang Lin, Jiun-In Guo:
A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding. ISCAS (6) 2005: 6110-6113
2004
[c21]
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  - conf/icmcs/ChangTCLG04
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Tai-Lun Chang, Ying-Ming Tsai, Chih-Da Chien, Chien-Chang Lin, Jiun-In Guo:
A high-performance MPEG4 bitstream processing core. ICME 2004: 467-470
[c18]
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  - conf/iscas/ChienLGC04
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Chih-Da Chien, Chien-Chang Lin, Jiun-In Guo, Tien-Fu Chen:
A power-aware IP core generator for the one-dimensional discrete Fourier transform. ISCAS (3) 2004: 637-640
2003
[c15]
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  - conf/iscas/GuoCL03
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Jiun-In Guo, Chih-Da Chien, Chien-Chang Lin:
A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining. ISCAS (5) 2003: 293-296
2002
[j5]
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  - journals/jcsc/GuoLC02
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Jiun-In Guo, Chien-Chang Lin, Chih-Da Chien:
A Low-Power Parameterized Hardware Design for the One-Dimensional Discrete Fourier Transform of Variable Lengths. J. Circuits Syst. Comput. 11(4): 405-428 (2002)
[c11]
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  - conf/iscas/GuoL02
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Jiun-In Guo, Chien-Chang Lin:
A new hardware efficient design for the one dimensional discrete Fourier transform. ISCAS (5) 2002: 549-552

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