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Greg J. Michaelson

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Deepayan Bhowmik

> Home > Persons > Greg J. Michaelson

Publications

2019
[j38]
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  - journals/jimaging/GarciaBSMW19
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  - https://dblp.org/rec/journals/jimaging/GarciaBSMW19
Paulo Garcia, Deepayan Bhowmik, Robert J. Stewart, Greg Michaelson, Andrew M. Wallace:
Optimized Memory Allocation and Power Minimization for FPGA-Based Image Processing. J. Imaging 5(1): 7 (2019)
2018
[j35]
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  - journals/trets/StewartDMGBW18
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  - https://dblp.org/rec/journals/trets/StewartDMGBW18
Rob Stewart, Kirsty Duncan, Greg Michaelson, Paulo Garcia, Deepayan Bhowmik, Andrew M. Wallace:
RIPL: A Parallel Image Processing Language for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 11(1): 7:1-7:24 (2018)
[c49]
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  - conf/arc/GarciaBWSM18
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Paulo Garcia, Deepayan Bhowmik, Andrew M. Wallace, Robert J. Stewart, Greg Michaelson:
Area-Energy Aware Dataflow Optimisation of Visual Tracking Systems. ARC 2018: 523-536
2017
[j33]
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  - journals/vlsisp/StewartBWM17
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Robert J. Stewart, Deepayan Bhowmik, Andrew M. Wallace, Greg Michaelson:
Profile Guided Dataflow Transformation for FPGAs and CPUs. J. Signal Process. Syst. 87(1): 3-20 (2017)
[c46]
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  dblp key:
  - conf/dasip/BhowmikGWSM17
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  - https://dblp.org/rec/conf/dasip/BhowmikGWSM17
Deepayan Bhowmik, Paulo Garcia, Andrew M. Wallace, Robert J. Stewart, Greg Michaelson:
Power efficient dataflow design for a heterogeneous smart camera architecture. DASIP 2017: 1-6
2016
[c44]
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  - conf/ica3pp/StewartMBGW16
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  - https://dblp.org/rec/conf/ica3pp/StewartMBGW16
Robert J. Stewart, Greg J. Michaelson, Deepayan Bhowmik, Paulo Garcia, Andy Wallace:
A Dataflow IR for Memory Efficient RIPL Compilation to FPGAs. ICA3PP Workshops 2016: 174-188
2015
[i1]
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  - journals/corr/StewartBMW15
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Robert J. Stewart, Deepayan Bhowmik, Greg Michaelson, Andrew M. Wallace:
RIPL: An Efficient Image Processing DSL for FPGAs. CoRR abs/1508.07136 (2015)
2014
[c42]
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  - conf/globalsip/BhowmikWSQM14
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  - https://dblp.org/rec/conf/globalsip/BhowmikWSQM14
Deepayan Bhowmik, Andrew M. Wallace, Robert J. Stewart, Xinyuan Qian, Greg J. Michaelson:
Profile driven dataflow optimisation of mean shift visual tracking. GlobalSIP 2014: 1-5

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