Ramón Ruiz Merino

◀ ▶ joint publications with Ginés Doménech-Asensi

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Publications

2023
[c17]
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Ginés Doménech-Asensi, Ramón Ruiz Merino, Juan Zapata-Pérez, José Ángel Díaz-Madrid:
A 12T SRAM in-Memory Computing differential current architecture for CNN implementations. ISCAS 2023: 1-5
2021
[j4]
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  - journals/cssp/Diaz-MadridDMZM21
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José Ángel Díaz-Madrid, Ginés Doménech-Asensi, J. Javier Martínez-Álvarez, Juan Zapata-Pérez, Ramón Ruiz Merino:
Joint Implementation of the Sharing OTA and Bias Current Regulation Techniques in an 11-Bit 10 MS/s Pipelined ADC. Circuits Syst. Signal Process. 40(2): 515-528 (2021)
2020
[j3]
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  - journals/jrtip/Domenech-Asensi20
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Ginés Doménech-Asensi, Juan Zapata-Pérez, Ramón Ruiz Merino, José-Alejandro López Alcantud, José Ángel Díaz-Madrid, Víctor Manuel Brea Sánchez, Paula López:
All-hardware SIFT implementation for real-time VGA images feature extraction. J. Real Time Image Process. 17(2): 371-382 (2020)
[c16]
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José Ángel Díaz-Madrid, Ginés Doménech-Asensi, Ramón Ruiz Merino, Juan Zapata-Pérez, José Javier Martínez:
Mixed Signal Multiply and Adder Parallel Circuit for Deep Learning Convolution Operations. ISCAS 2020: 1-5
2018
[j2]
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  - journals/ijcta/Rubio-IbanezRDM18
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Pablo Rubio-Ibáñez, Ramón Ruiz Merino, Ginés Doménech-Asensi, J. Javier Martínez-Álvarez, Juan Zapata-Pérez, José Ángel Díaz-Madrid, José-Alejandro López Alcantud:
An all-hardware implementation of the subpixel refinement stage in SIFT algorithm. Int. J. Circuit Theory Appl. 46(9): 1690-1702 (2018)
[c15]
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  - conf/icdsc/Carmona-GalanFR18
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Ricardo Carmona-Galán, Jorge Fernández-Berni, Ángel Rodríguez-Vázquez, Paula López Martinez, Víctor Manuel Brea Sánchez, Diego Cabello Ferrer, Ginés Doménech-Asensi, Ramón Ruiz Merino, Juan Zapata-Pérez:
Results of 'iCaveats', a Project on the Integration of Architectures and Components for Embedded Vision. ICDSC 2018: 24:1-24:2
2013
[j1]
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  - journals/ijcta/Domenech-Asensi13
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Ginés Doménech-Asensi, José Ángel Díaz-Madrid, Ramón Ruiz Merino:
Synthesis of CMOS analog circuit VHDL-AMS descriptions using parameterizable macromodels. Int. J. Circuit Theory Appl. 41(7): 732-742 (2013)
2012
[c14]
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  - conf/icecsys/Domenech-AsensiMIZMAMFCD12
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Ginés Doménech-Asensi, F. Martinez-Viviente, J. Illade-Quinteiro, Juan Zapata-Pérez, Ramón Ruiz Merino, José-Alejandro López Alcantud, Juan Martínez-Alajarín, Francisco J. Fernández-Luque, Juan M. Carrillo, Miguel Angel Domínguez:
A fourth order CMOS band pass filter for PIR sensors. ICECS 2012: 268-271
2009
[c13]
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  - conf/date/Diaz-MadridNHDR09
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José Ángel Díaz-Madrid, Harald Neubauer, Hans Hauer, Ginés Doménech-Asensi, Ramón Ruiz Merino:
Power reduction of a 12-bit 40-MS/s pipeline ADC exploiting partial amplifier sharing. DATE 2009: 369-373
2008
[c11]
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  - conf/iscas/Domenech-AsensiHRD08
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Ginés Doménech-Asensi, Juan Hinojosa, Ramón Ruiz Merino, José Ángel Díaz-Madrid:
Accurate and reusable macromodeling technique using a fuzzy-logic approach. ISCAS 2008: 508-511
2006
[c6]
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  - conf/fpl/Domenech-AsensiMMA06
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Ginés Doménech-Asensi, Juan Martínez-Alajarín, Ramón Ruiz Merino, José-Alejandro López Alcantud:
Synthesis on FPAA of a Smart Sthetoscope Analog Subsystem. FPL 2006: 1-5
2005
[c5]
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  - conf/iwinac/Domenech-AsensiAM05
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Ginés Doménech-Asensi, José-Alejandro López Alcantud, Ramón Ruiz Merino:
Description and Simulation of Bio-inspired Systems Using VHDL-AMS. IWINAC (2) 2005: 357-365
2003
[c4]
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  - conf/iwann/Domenech-AsensiRHD03
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Ginés Doménech-Asensi, Ramón Ruiz Merino, Hans Hauer, José Ángel Díaz-Madrid:
Current Mode CMOS Synthesis of a Motor-Control Neural System. IWANN (2) 2003: 25-32

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