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Shi-Yu Huang
- > Home > Persons > Shi-Yu Huang
Publications
- 2023
- [c85]Yi-Hsuan Lee, Wei-Hao Chen, Shi-Yu Huang:
Self-Sufficient Clock Jitter Measurement Methodology Using Dithering-Based Calibration. ITC-Asia 2023: 1-6 - [c84]Chen-Lin Tsai, Shi-Yu Huang:
Trustworthy Lifetime Prediction by Aging History Analysis and Multi-Level Stress Test. ITC-Asia 2023: 1-6 - 2022
- [j54]Wei-Hao Chen, Shi-Yu Huang:
On-Chip Jitter Learning for PLL. IEEE Des. Test 39(4): 58-63 (2022) - [c80]Chen-Lin Tsai, Shi-Yu Huang:
Just-Enough Stress Test for Infant-Mortality Screening Using Speed Binning. ITC 2022: 137-144 - 2021
- [j50]Wei Chu, Shi-Yu Huang:
Online Safety Checking for Delay Locked Loops via Embedded Phase Error Monitor. IEEE Trans. Emerg. Top. Comput. 9(2): 735-744 (2021) - [c79]Yi-Hsuan Lee, Shi-Yu Huang:
Rigorous Test Flow for PLL to Identify Weak Devices. ITC-Asia 2021: 1-6 - [c78]Chen-Lin Tsai, Wei-Hao Chen, Shi-Yu Huang:
A Duty-Cycle Monitor Supporting A Wide Frequency Range of Clock Signal. ITC-Asia 2021: 1-6 - 2020
- [c75]Wei Chu, Wei-Hao Chen, Shi-Yu Huang:
Duty-Cycle Correction For A Super-Wide Frequency Range from 10MHz to 1.2GHz. ICCD 2020: 457-460 - [c73]Wei-Hao Chen, Chu-Chun Hsu, Shi-Yu Huang:
Rapid PLL Monitoring By A Novel min-MAX Time-to-Digital Converter. ITC 2020: 1-8 - 2019
- [j47]Zheng-Hong Zhang, Wei Chu, Shi-Yu Huang:
A Ping-Pong Methodology for Boosting the Resilience of Cell-Based Delay-Locked Loop. IEEE Access 7: 97928-97937 (2019) - [c71]Zheng-Hong Zhang, Wei Chu, Shi-Yu Huang:
The Ping-Pong Tunable Delay Line In A Super-Resilient Delay-Locked Loop. DAC 2019: 231 - [c70]Wei Chu, Shi-Yu Huang:
Overall Strategy for Online Clock System Checking Supporting Heterogeneous Integration. ITC 2019: 1-10 - [c68]Wei Chu, Shi-Yu Huang:
Online Testing of Clock Delay Faults in a Clock Network. ITC-Asia 2019: 163-168 - [c67]Wei Chu, Shi-Yu Huang:
A Cell-Based Wide-Frequency-Range DLL Supporting Fast Frequency Scaling. NEWCAS 2019: 1-4 - 2005
- [j9]Ying-Chieh Chuang, Shih-Fang Chen, Shi-Yu Huang, Ya-Chin King:
Low-cost logarithmic CMOS image sensing by nonlinear analog-to-digital conversion. IEEE Trans. Consumer Electron. 51(4): 1212-1217 (2005)
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