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Reiner W. Hartenstein
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Publications
- 2006
- [j23]Mauricio Ayala-Rincón, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein:
Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic. ACM Trans. Design Autom. Electr. Syst. 11(2): 251-281 (2006) - [c76]Carlos Morra, M. Sackmann, Sunil Shukla, Jürgen Becker, Reiner W. Hartenstein:
From Equation to VHDL: Using Rewriting Logic for Automated Function Generation. FPL 2006: 1-4 - [c74]Peter Wintermayr, Reiner W. Hartenstein, Heinrich Meyr, Steve Leibson:
Flexibility and low power: a contradiction in terms? ISLPED 2006: 375 - [c73]Carlos Morra, M. Sackmann, Jürgen Becker, Reiner W. Hartenstein:
Using Rewriting Logic to Generate Different Implementations of Polynomial Approximations in Coarse-Grained Architectures. ReCoSoC 2006: 46-51 - 2005
- [c71]Carlos Morra, Jürgen Becker, Mauricio Ayala-Rincón, Reiner W. Hartenstein:
FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations. FPL 2005: 25-30 - 2004
- [c69]Mauricio Ayala-Rincón, Ricardo P. Jacobi, Luis Gustavo A. Carvalho, Carlos H. Llanos, Reiner W. Hartenstein:
Modeling and prototyping dynamically reconfigurable systems for efficient computation of dynamic programming methods by rewriting-logic. SBCCI 2004: 248-253 - [c67]Ricardo P. Jacobi, Mauricio Ayala-Rincón, Luis Gustavo A. Carvalho, Carlos H. Llanos, Reiner W. Hartenstein:
Reconfigurable Systems for Sequence Alignment and for General Dynamic Programming. WOB 2004: 25-32 - 2003
- [j22]Jürgen Becker, Reiner W. Hartenstein:
Configware and morphware going mainstream. J. Syst. Archit. 49(4-6): 127-142 (2003) - [c66]Mauricio Ayala-Rincón, Ricardo P. Jacobi, Carlos H. Llanos, Reiner W. Hartenstein:
Using Rewriting-Logic Notation for Funcional Verification in Data-Stream Based Reconfigurable Computing. FDL 2003: 492-504 - [c64]Mauricio Ayala-Rincón, Rodrigo Borges Nogueira, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein:
Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic. SBCCI 2003: 205-210 - [c63]Mauricio Ayala-Rincón, Rodrigo Borges Nogueira, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein:
Efficient Computation of Algebraic Operations over Dynamically Reconfigurable Systems Specified by Rewriting-Logic Environments. SCCC 2003: 60- - 2002
- [j21]Mauricio Ayala-Rincón, Reiner W. Hartenstein, Rinaldi Maya Neto, Ricardo P. Jacobi, Carlos H. Llanos:
Architectural Specification, Exploration and Simulation Through Rewriting-Logic. Rev. Colomb. de Computación 3(2) (2002) - [c60]Michael Herz, Reiner W. Hartenstein, Miguel Miranda, Erik Brockmeyer, Francky Catthoor:
Memory addressing organization for stream-based reconfigurable computing. ICECS 2002: 813-817 - [c59]Mauricio Ayala-Rincón, Rinaldi Maya Neto, Ricardo P. Jacobi, Carlos H. Llanos, Reiner W. Hartenstein:
Applying ELAN Strategies in Simulating Processors over Simple Architectures. WRS 2002: 84-99 - 2000
- [c55]Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger:
KressArray Xplorer: a new CAD environment to optimize reconfigurable datapath array. ASP-DAC 2000: 163-168 - [c54]Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger:
Synthesis and domain-specific optimization of KressArray-based reconfigurable computing engines (poster abstract). FPGA 2000: 222 - [c53]Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger:
Generation of Design Suggestions for Coarse-Grain Reconfigurable Architectures. FPL 2000: 389-399 - [c52]Reiner W. Hartenstein, Thomas Hoffmann, Ulrich Nageldinger:
Design-Space Exploration of Low Power Coarse Grained Reconfigurable Datapath Array Architectures. PATMOS 2000: 118-128 - 1999
- [c51]Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger, Thomas Hoffmann:
An Internet Based Development Framework for Reconfigurable Computing. FPL 1999: 155-164 - [c50]Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger:
Mapping Applications onto Reconfigurable Kress Arrays. FPL 1999: 385-390 - [c49]Reiner W. Hartenstein, Veljko M. Milutinovic:
Configware: From Glue Logic Synthesis to Reconfigurable Computing Systems- Introduction. HICSS 1999 - [e5]Patrick Lysaght, James Irvine, Reiner W. Hartenstein:
Field-Programmable Logic and Applications, 9th International Workshop, FPL'99, Glasgow, UK, August 30 - September 1, 1999, Proceedings. Lecture Notes in Computer Science 1673, Springer 1999, ISBN 3-540-66457-2 [contents] - 1998
- [c48]Jürgen Becker, Reiner W. Hartenstein, Michael Herz, Ulrich Nageldinger:
Parallelization in Co-Compilation for Configurable Accelerators. ASP-DAC 1998: 23-33 - [c47]Reiner W. Hartenstein, Michael Herz, Frank Gilbert:
Designing for Xilinx XC6200 FPGAs. FPL 1998: 29-38 - [c46]Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger:
Exploiting Contemporary Memory Techniques in Reconfigurable Accelerators. FPL 1998: 189-198 - [c44]Reiner W. Hartenstein, Michael Herz, Thomas Hoffmann, Ulrich Nageldinger:
On Reconfigurable Co-processing Units. IPPS/SPDP Workshops 1998: 67-72 - [c43]Jürgen Becker, Reiner W. Hartenstein:
Real-Time Prototyping in Microprocessor/Accelerator Symbiosis. International Workshop on Rapid System Prototyping 1998: 32-38 - 1997
- [j20]William H. Mangione-Smith, Brad Hutchins, David L. Andrews, André DeHon, Carl Ebeling, Reiner W. Hartenstein, Oskar Mencer, John Morris, Krishna V. Palem, Viktor K. Prasanna, Henk A. E. Spaanenburg:
Seeking Solutions in Configurable Computing. Computer 30(12): 38-43 (1997) - [c42]Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger:
A Novel Universal Sequencer Hardware. ARCS 1997: 143-152 - [c41]Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger:
A Novel Sequencer Hardware for Application Specific Computing. ASAP 1997: 392-401 - [c40]Reiner W. Hartenstein, Jürgen Becker:
Performance Analysis in CoDe-X Partitioning for Structural Programmable Accelerators. CODES 1997: 141-145 - [c39]Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Ulrich Nageldinger:
Data scheduling to increase performance of parallel accelerators. FPL 1997: 294-303 - [c38]Rainer Kress, Reiner W. Hartenstein, Ulrich Nageldinger:
An operating system for custom computing machines based on the Xputer paradigm. FPL 1997: 304-313 - [c37]Reiner W. Hartenstein, Jürgen Becker:
A Two-level Co-Design Framework for Xputer-based data-driven reconfigurable Accelerators. HICSS (5) 1997: 125-134 - [c36]Reiner W. Hartenstein, Jürgen Becker:
Hardware/Software Co-Design for Data-Driven Xputer-based Accelerators. VLSI Design 1997: 146-150 - 1996
- [j19]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig:
High-performance computing using a reconfigurable accelerator. Concurr. Pract. Exp. 8(6): 429-443 (1996) - [c35]Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger:
A Synthesis System For Bus-Based Wavefront Array Architectures. ASAP 1996: 274-283 - [c34]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress:
Two-level Partitioning of Image Processing Algorithms for the Parallel Map-oriented Machine. CODES 1996: 77-84 - [c33]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress:
Two-Level Hardware/Software Partitioning Using CoDe-X. ECBS 1996: 395- - [c32]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress:
An Embedded Accelerator for Real-Time Image Processing. RTS 1996: 83-88 - [c31]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress:
Custom Computing Machines vs. Hardware/Software Codesign: From a globalized point of view. FPL 1996: 65-76 - [c30]Reiner W. Hartenstein, Jürgen Becker, Michael Herz, Rainer Kress, Ulrich Nageldinger:
A Partitioning Programming Environment for a Novel Parallel Architecture. IPPS 1996: 544-548 - [c29]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig:
CoDe-C: A Novel Two-Level Hardware/Software Co-Design Framework. VLSI Design 1996: 81-84 - [e3]Reiner W. Hartenstein, Manfred Glesner:
Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, 6th International Workshop on Field-Programmable Logic, FPL '96, Darmstadt, Germany, September 23-25, 1996, Proceedings. Lecture Notes in Computer Science 1142, Springer 1996, ISBN 3-540-61730-2 [contents] - 1995
- [c28]Reiner W. Hartenstein, Jürgen Becker, Rainer Kress, Helmut Reinig, Karin Schmidt:
A Parallelizing Compilation Method for the Map-oriented Machine. ASAP 1995: 129-132 - [c27]Reiner W. Hartenstein, Rainer Kress:
A datapath synthesis system for the reconfigurable datapath architecture. ASP-DAC 1995 - [c26]Reiner W. Hartenstein, Karin Schmidt:
Combining structural and procedural programming by parallelizing compilation. SAC 1995: 130-134 - 1994
- [c25]Reiner W. Hartenstein, Rainer Kress, Helmut Reinig:
A dynamically reconfigurable wavefront array architecture for evaluation of expressions. ASAP 1994: 404-414 - [c24]Reiner W. Hartenstein, Rainer Kress, Helmut Reinig:
A New FPGA Architecture for Word-Oriented Datapaths. FPL 1994: 144-155 - [c23]Andreas Ast, Jürgen Becker, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt:
Data-Procedural Languages for FPL-based Machines. FPL 1994: 183-195 - 1993
- [j16]Rainer Kress, Elmar U. K. Melcher, Reiner W. Hartenstein, Michel Dana:
CMOS interconnect modelling for timing analysis. Microprocess. Microprogramming 37(1-5): 7-10 (1993) - 1992
- [j15]Reiner W. Hartenstein, Alexander G. Hirschbiel, Karin Schmidt, M. Weber:
A novel paradigm of parallel computation and its use to implement simple high-performance hardware. Future Gener. Comput. Syst. 7(2-3): 181-198 (1992) - [c22]Andreas Ast, Reiner W. Hartenstein, Rainer Kress, Helmut Reinig, Karin Schmidt:
Novel High Performance Machine Paradigms and Fast- Turnaround ASIC Design Methods. FPL 1992: 211-217 - [c21]Joachim Blödel, Markus Brandstetter, Peter Conradi, Walter Drangmeister, Reiner W. Hartenstein, Dietmar Schroeder:
An Information Model Describing the Exchange of IC Technology Data. Electronic Design Automation Frameworks 1992: 9-19 - 1990
- [c20]Reiner W. Hartenstein, Alexander G. Hirschbiel, M. Weber:
Xputers: An Open Family of Non-Von Neumann Architectures. ARCS 1990: 45-58 - [c19]Reiner W. Hartenstein, Alexander G. Hirschbiel, M. Weber:
A Novel Paradigm of Parallel Computation and its Use to Implement Simple High Performance Hardware. CONPAR 1990: 51-62 - [c18]Reiner W. Hartenstein, Alexander G. Hirschbiel, Michael Riedmüller, Karin Schmidt, M. Weber:
Automatic Synthesis of Cheap Hardware Accelerators for Signal Processing and Image Processing. DAGM-Symposium 1990: 404-417 - [c17]Reiner W. Hartenstein, Alexander G. Hirschbiel, M. Weber:
The Machine Paradigm of Xputers and its Application to Digital Signal Processing Acceleration. ICPP (1) 1990: 609-610 - [c16]Reiner W. Hartenstein, Alexander G. Hirschbiel, M. Weber:
Xputers: very high throughput by innovative computing principles. Jerusalem Conference on Information Technology 1990: 43-50 - [c15]Reiner W. Hartenstein, Alexander G. Hirschbiel, Karin Lemmert, Michael Riedmüller, Karin Schmidt, M. Weber:
Xputer use in image processing and digital signal processing. VCIP 1990 - 1989
- [j13]Reiner W. Hartenstein, Karin Lemmert, Michael Riedmüller:
Synthesis of systolic architectures using the SYS3 system. Microprocessing and Microprogramming 27(1-5): 479-486 (1989) - 1988
- [j11]Joachim Blödel, Reiner W. Hartenstein, Wolfgang Nebel, Michael Ryba:
A technology description method for generalized layout / circuit relations. Microprocess. Microprogramming 23(1-5): 15-20 (1988) - [c14]Reiner W. Hartenstein, Michael Ryba:
Partitionierungsschemata für Rechnerstrukturen. GI Jahrestagung (2) 1988: 246-262 - 1987
- [j9]Reiner W. Hartenstein, Alexander Hirschbiel, M. Weber:
A flexible architecture for image processing. Microprocess. Microprogramming 21(1-5): 65-71 (1987)
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