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2020 – today
- 2020
[j4]Dong-Shin Jo
, Ba-Ro-Saim Sung, Min-Jae Seo, Woo-Cheol Kim, Seung-Tak Ryu:
A 40-nm CMOS 7-b 32-GS/s SAR ADC With Background Channel Mismatch Calibration. IEEE Trans. Circuits Syst. II Express Briefs 67-II(4): 610-614 (2020)
2010 – 2019
- 2016
- [j3]Si-Nai Kim, Mee-Ran Kim, Ba-Ro-Saim Sung, Hyun-Wook Kang, Min-Hyung Cho, Seung-Tak Ryu:
A SUC-Based Full-Binary 6-bit 3.1-GS/s 17.7-mW Current-Steering DAC in 0.038 mm2. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 794-798 (2016) - 2015
- [j2]Jong-In Kim, Dong-Ryeol Oh, Dong-Shin Jo, Ba-Ro-Saim Sung, Seung-Tak Ryu:
A 65 nm CMOS 7b 2 GS/s 20.7 mW Flash ADC With Cascaded Latch Interpolation. IEEE J. Solid State Circuits 50(10): 2319-2330 (2015) - [c1]Ba-Ro-Saim Sung, Dong-Shin Jo, Il-Hoon Jang, Dong-Suk Lee, Yong-Sang You, Yong-Hee Lee, Ho-Jin Park, Seung-Tak Ryu:
26.4 A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS. ISSCC 2015: 1-3 - 2013
- [j1]Jong-In Kim, Ba-Ro-Saim Sung, Wan Kim, Seung-Tak Ryu:
A 6-b 4.1-GS/s Flash ADC With Time-Domain Latch Interpolation in 90-nm CMOS. IEEE J. Solid State Circuits 48(6): 1429-1441 (2013)
Coauthor Index
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