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Semantic ScholarFrank K. Gürkaynak
Frank Kagan Gürkaynak
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2010 – today
- 2018
[c39]Robert Schilling, Thomas Unterluggauer, Stefan Mangard, Frank K. Gürkaynak, Michael Muehlberghuber, Luca Benini:
High speed ASIC implementations of leakage-resilient cryptography. DATE 2018: 1259-1264- [c38]Florian Glaser, Stefan Mach, Abbas Rahimi, Frank K. Gürkaynak, Qiuting Huang, Luca Benini:
An 826 MOPS, 210uW/MHz Unum ALU in 65 nm. ISCAS 2018: 1-5 - [i8]Fabian Schuiki, Michael Schaffner, Frank K. Gürkaynak, Luca Benini:
A Scalable Near-Memory Architecture for Training Deep Neural Networks on Large In-Memory Datasets. CoRR abs/1803.04783 (2018) - 2017
- [j13]Michael Gautschi, Michael Schaffner, Frank K. Gürkaynak, Luca Benini:
An Extended Shared Logarithmic Unit for Nonlinear Function Kernel Acceleration in a 65-nm CMOS Multicore Cluster. J. Solid-State Circuits 52(1): 98-112 (2017) - [j12]Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Philippe Flatresse, Luca Benini:
Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. IEEE Micro 37(5): 20-31 (2017) - [j11]Francesco Conti, Robert Schilling, Pasquale Davide Schiavone, Antonio Pullini, Davide Rossi, Frank Kagan Gürkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard, Luca Benini:
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics. IEEE Trans. on Circuits and Systems 64-I(9): 2481-2494 (2017) - [j10]Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flamand, Frank K. Gürkaynak, Luca Benini:
Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices. IEEE Trans. VLSI Syst. 25(10): 2700-2713 (2017) - [c37]Thomas Unterluggauer, Thomas Korak, Stefan Mangard, Robert Schilling, Luca Benini, Frank K. Gürkaynak, Michael Muehlberghuber:
Leakage Bounds for Gaussian Side Channels. CARDIS 2017: 88-104 - [c36]Frank K. Gürkaynak, Robert Schilling, Michael Muehlberghuber, Francesco Conti, Stefan Mangard, Luca Benini:
Multi-core data analytics SoC with a flexible 1.76 Gbit/s AES-XTS cryptographic accelerator in 65 nm CMOS. CS2@HiPEAC 2017: 19-24 - [i7]Florian Glaser, Stefan Mach, Abbas Rahimi, Frank K. Gürkaynak, Qiuting Huang, Luca Benini:
An 826 MOPS, 210 uW/MHz Unum ALU in 65 nm. CoRR abs/1712.01021 (2017) - [i6]Thomas Unterluggauer, Thomas Korak, Stefan Mangard, Robert Schilling, Luca Benini, Frank K. Gürkaynak, Michael Muehlberghuber:
Leakage Bounds for Gaussian Side Channels. IACR Cryptology ePrint Archive 2017: 992 (2017) - 2016
- [j9]Michael Schaffner, Frank K. Gürkaynak, Pierre Greisen, Hubert Kaeslin, Luca Benini, Aljosa Smolic:
Hybrid ASIC/FPGA System for Fully Automatic Stereo-to-Multiview Conversion Using IDW. IEEE Trans. Circuits Syst. Video Techn. 26(11): 2093-2108 (2016) - [c35]Michael Schaffner, Michael Gautschi, Frank K. Gürkaynak, Luca Benini:
Accuracy and Performance Trade-Offs of Logarithmic Number Units in Multi-Core Clusters. ARITH 2016: 95-103 - [c34]Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Fady Abouzeid, Philippe Flatresse, Luca Benini:
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. COOL Chips 2016: 1-3 - [c33]Youri Popoff, Florian Scheidegger, Michael Schaffner, Michael Gautschi, Frank K. Gürkaynak, Luca Benini:
High-efficiency logarithmic number unit design based on an improved cotransformation scheme. DATE 2016: 1387-1392 - [c32]Vincent Camus, Jeremy Schlachter, Christian Enz, Michael Gautschi, Frank K. Gürkaynak:
Approximate 32-bit floating-point unit design with 53% power-area product reduction. ESSCIRC 2016: 465-468 - [c31]Michael Gautschi, Michael Schaffner, Frank K. Gürkaynak, Luca Benini:
4.6 A 65nm CMOS 6.4-to-29.2pJ/FLOP@0.8V shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster. ISSCC 2016: 82-83 - [i5]Michael Gautschi, Pasquale Davide Schiavone, Andreas Traber, Igor Loi, Antonio Pullini, Davide Rossi, Eric Flamand, Frank K. Gürkaynak, Luca Benini:
A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devices. CoRR abs/1608.08376 (2016) - [i4]Francesco Conti, Robert Schilling, Pasquale Davide Schiavone, Antonio Pullini, Davide Rossi, Frank Kagan Gürkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard, Luca Benini:
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics. CoRR abs/1612.05974 (2016) - 2015
- [c30]Michael Schaffner, Frank K. Gürkaynak, Aljoscha Smolic, Luca Benini:
DRAM or no-DRAM?: exploring linear solver architectures for image domain warping in 28 nm CMOS. DATE 2015: 707-712 - [c29]Michael Schaffner, Frank K. Gürkaynak, Hubert Kaeslin, Luca Benini, Aljosa Smolic:
Automatic multiview synthesis - Towards a mobile system on a chip. VCIP 2015: 1-4 - [c28]Michael Schaffner, Frank K. Gürkaynak, Hubert Kaeslin, Luca Benini, Aljosa Smolic:
Automatic multiview synthesis - Prototype demo. VCIP 2015: 1 - 2014
- [c27]Michael Schaffner, Frank K. Gürkaynak, Aljoscha Smolic, Hubert Kaeslin, Luca Benini:
An Approximate Computing Technique for Reducing the Complexity of a Direct-Solver for Sparse Linear Systems in Real-Time Video Processing. DAC 2014: 132:1-132:6 - [c26]Christoph Keller, Frank K. Gürkaynak, Hubert Kaeslin, Norbert Felber:
Dynamic memory-based physically unclonable function for the generation of unique identifiers and true random numbers. ISCAS 2014: 2740-2743 - 2013
- [c25]Michael Muehlberghuber, Frank K. Gürkaynak, Thomas Korak, Philipp Dunst, Michael Hutter:
Red team vs. blue team hardware trojan analysis: detection of a hardware trojan on an actual ASIC. HASP@ISCA 2013: 1 - [c24]Michael Schaffner, Pascal Hager, Lukas Cavigelli, Pierre Greisen, Frank K. Gürkaynak, Hubert Kaeslin:
A real-time 720p feature extraction core based on Semantic Kernels Binarized. VLSI-SoC 2013: 27-32 - [c23]Michael Schaffner, Pascal A. Hager, Lukas Cavigelli, Z. Fang, Pierre Greisen, Frank K. Gürkaynak, Aljoscha Smolic, Hubert Kaeslin, Luca Benini:
A Complete Real-Time Feature Extraction and Matching System Based on Semantic Kernels Binarized. VLSI-SoC (Selected Papers) 2013: 144-167 - 2012
- [c22]Jeremy Constantin, Andreas Burg, Frank K. Gürkaynak:
Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture. ASAP 2012: 117-124 - [c21]Michael Muehlberghuber, Christoph Keller, Frank K. Gürkaynak, Norbert Felber:
FPGA-Based High-Speed Authenticated Encryption System. VLSI-SoC (Selected Papers) 2012: 1-20 - [c20]Pierre Greisen, Michael Schaffner, Danny Luu, Val Mikos, Simon Heinzle, Frank K. Gürkaynak, Aljoscha Smolic:
Spatially-Varying Image Warping: Evaluations and VLSI Implementations. VLSI-SoC (Selected Papers) 2012: 64-87 - [c19]Pierre Greisen, Richard Emler, Michael Schaffner, Simon Heinzle, Frank K. Gürkaynak:
A general-transformation EWA view rendering engine for 1080p video in 130 nm CMOS. VLSI-SoC 2012: 105-110 - [i3]Jeremy Constantin, Andreas Burg, Frank K. Gürkaynak:
Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-bit Microcontroller Architecture. IACR Cryptology ePrint Archive 2012: 50 (2012) - 2010
- [j8]Deniz Karakoyunlu, Frank Kagan Gürkaynak, Berk Sunar, Yusuf Leblebici:
Efficient and side-channel-aware implementations of elliptic curve cryptosystems over prime fields. IET Information Security 4(1): 30-43 (2010) - [c18]Luca Henzen, Pietro Gendotti, Patrice Guillet, Enrico Pargaetzi, Martin Zoller, Frank K. Gürkaynak:
Developing a Hardware Evaluation Method for SHA-3 Candidates. CHES 2010: 248-263
2000 – 2009
- 2009
- [j7]Milos Krstic, Xin Fan, Eckhard Grass, Frank K. Gürkaynak:
GALS for Bursty Data Transfer based on Clock Coupling. Electr. Notes Theor. Comput. Sci. 245: 103-113 (2009) - [j6]Omer Can Akgun, Frank K. Gürkaynak, Yusuf Leblebici:
A current sensing completion detection method for asynchronous pipelines operating in the sub-threshold regime. I. J. Circuit Theory and Applications 37(2): 203-220 (2009) - [j5]Francesco Regazzoni, Thomas Eisenbarth, Axel Poschmann, Johann Großschädl, Frank K. Gürkaynak, Marco Macchetti, Zeynep Toprak Deniz, Laura Pozzi, Christof Paar, Yusuf Leblebici, Paolo Ienne:
Evaluating Resistance of MCML Technology to Power Analysis Attacks Using a Simulation-Based Methodology. Trans. Computational Science 4: 230-243 (2009) - [j4]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Seyed Hosein Attarzadeh Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. TRETS 2(2): 13:1-13:36 (2009) - [i2]Daniel V. Bailey, Brian Baldwin, Lejla Batina, Daniel J. Bernstein, Peter Birkner, Joppe W. Bos, Gauthier Van Damme, Giacomo de Meulenaer, Junfeng Fan, Tim Güneysu, Frank K. Gürkaynak, Thorsten Kleinjung, Tanja Lange, Nele Mentens, Christof Paar, Francesco Regazzoni, Peter Schwabe, Leif Uhsadel:
The Certicom Challenges ECC2-X. IACR Cryptology ePrint Archive 2009: 466 (2009) - [i1]Daniel V. Bailey, Lejla Batina, Daniel J. Bernstein, Peter Birkner, Joppe W. Bos, Hsieh-Chung Chen, Chen-Mou Cheng, Gauthier Van Damme, Giacomo de Meulenaer, Luis J. Dominguez Perez, Junfeng Fan, Tim Güneysu, Frank K. Gürkaynak, Thorsten Kleinjung, Tanja Lange, Nele Mentens, Ruben Niederhagen, Christof Paar, Francesco Regazzoni, Peter Schwabe, Leif Uhsadel, Anthony Van Herrewege, Bo-Yin Yang:
Breaking ECC2K-130. IACR Cryptology ePrint Archive 2009: 541 (2009) - 2008
- [c17]Seyed Hosein Attarzadeh Niaki, Alessandro Cevrero, Philip Brisk, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne:
Design space exploration for field programmable compressor trees. CASES 2008: 207-216 - [c16]Stéphane Badel, Erdem Guleyupoglu, Ozgur Inac, Anna Pena Martinez, Paolo Vietti, Frank K. Gürkaynak, Yusuf Leblebici:
A Generic Standard Cell Design Methodology for Differential Circuit Styles. DATE 2008: 843-848 - [c15]Carlotta Guiducci, Alexandre Schmid, Frank K. Gürkaynak, Yusuf Leblebici:
Novel Front-End Circuit Architectures for Integrated Bio-Electronic Interfaces. DATE 2008: 1328-1333 - [c14]Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne:
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. FPGA 2008: 181-190 - [c13]Armin Tajalli, Frank K. Gürkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer:
Improving the power-delay product in SCL circuits using source follower output stage. ISCAS 2008: 145-148 - 2007
- [j3]Milos Krstic, Eckhard Grass, Frank K. Gürkaynak, Pascal Vivet:
Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook. IEEE Design & Test of Computers 24(5): 430-441 (2007) - [c12]Milos Stanisavljevic, Frank K. Gürkaynak, Alexandre Schmid, Yusuf Leblebici, Maria Gabrani:
Design and realization of a fault-tolerant 90nm CMOS cryptographic engine capable of performing under massive defect density. ACM Great Lakes Symposium on VLSI 2007: 204-207 - [c11]Milos Stanisavljevic, Frank Kagan Gürkaynak, Alexandre Schmid, Yusuf Leblebici, Maria Gabrani:
A 90nm CMOS cryptographic core with improved fault-tolerance in presence of massive defect density. Nano-Net 2007: 4 - 2006
- [b1]Frank Kagan Gürkaynak:
GALS system design: side channel attack secure cryptographic accelerators. ETH Zurich 2006, ISBN 3-86628-065-3, pp. 1-165 - [j2]Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
Design Challenges for a Differential-Power-Analysis Aware GALS-based AES Crypto ASIC. Electr. Notes Theor. Comput. Sci. 146(2): 133-149 (2006) - [c10]Frank K. Gürkaynak, Stephan Oetiker, Hubert Kaeslin, Norbert Felber, Wolfgang Fichtner:
GALS at ETH Zurich: Success or Failure. ASYNC 2006: 150-159 - 2004
- [c9]Frank K. Gürkaynak, Andreas Burg, Norbert Felber, Wolfgang Fichtner, D. Gasser, F. Hug, Hubert Kaeslin:
A 2 Gb/s balanced AES crypto-chip implementation. ACM Great Lakes Symposium on VLSI 2004: 39-44 - [c8]Siddika Berna Örs, Frank K. Gürkaynak, Elisabeth Oswald, Bart Preneel:
Power-Analysis Attack on an ASIC AES implementation. ITCC (2) 2004: 546-552 - 2003
- [c7]Thomas Villiger, Hubert Kaeslin, Frank K. Gürkaynak, Stephan Oetiker, Wolfgang Fichtner:
Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems. ASYNC 2003: 141-150 - [c6]Andreas Burg, Frank K. Gürkaynak, Hubert Kaeslin, Wolfgang Fichtner:
Variable delay ripple carry adder with carry chain interrupt detection. ISCAS (5) 2003: 113-116 - 2002
- [c5]Thomas Villiger, Stephan Oetiker, Frank K. Gürkaynak, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner:
A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems. ASYNC 2002: 181-189 - [c4]A. K. Lutz, J. Treichler, Frank K. Gürkaynak, Hubert Kaeslin, G. Basler, Antonia Erni, S. Reichmuth, P. Rommens, Stephan Oetiker, Wolfgang Fichtner:
2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis. CHES 2002: 144-158 - 2000
- [j1]Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici:
A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic. VLSI Design 2000(2): 115-128 (2000) - [c3]Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici:
A compact modular architecture for high-speed binary sorting. ICASSP 2000: 3339-3342 - [c2]Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici:
A compact modular architecture for the realization of high-speed binary sorting engines based on rank ordering. ISCAS 2000: 685-688
1990 – 1999
- 1999
- [c1]Ilhan Hatirnaz, Frank K. Gürkaynak, Yusuf Leblebici:
Realization of a programmable rank-order filter architecture using capacitive threshold logic gates. ISCAS (1) 1999: 435-438
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