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Jeremy Constantin

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2018
[c12]
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  - conf/iscas/BonettiCTB18
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Andrea Bonetti, Jeremy Constantin, Adam Ternan, Andreas Burg:
A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI. ISCAS 2018: 1-4
2017
[j3]
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  - journals/micro/RossiPLGGTCBPBC17
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Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Philippe Flatresse, Luca Benini:
Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. IEEE Micro 37(5): 20-31 (2017)
[j2]
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Jeremy Constantin, Raphael Houlmann, Nicholas Preyss, Nino Walenta, Hugo Zbinden, Pascal Junod, Andreas Burg:
An FPGA-Based 4 Mbps Secret Key Distillation Engine for Quantum Key Distribution Systems. Signal Processing Systems 86(1): 1-15 (2017)
2016
[c11]
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  - conf/coolchips/RossiPLGGTCBPBC16
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Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Fady Abouzeid, Philippe Flatresse, Luca Benini:
193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. COOL Chips 2016: 1-3
[c10]
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  - conf/dac/ConstantinBWCK16
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Jeremy Constantin, Andreas Peter Burg, Zheng Wang, Anupam Chattopadhyay, Georgios Karakonstantis:
Statistical fault injection for impact-evaluation of timing errors on application performance. DAC 2016: 13:1-13:6
[c9]
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  - conf/esscirc/ConstantinBTMSB16
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Jeremy Constantin, Andrea Bonetti, Adam Teman, Thomas Christoph Müller, Lorenz Schmid, Andreas Burg:
DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment. ESSCIRC 2016: 261-264
[c8]
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  - conf/iscas/GhanaatianWCTB16
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Reza Ghanaatian, Paul N. Whatmough, Jeremy Constantin, Adam Teman, Andreas Burg:
A low-power correlator for wakeup receivers with algorithm pruning through early termination. ISCAS 2016: 2667-2670
2015
[c7]
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  - conf/date/ConstantinWKCB15
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Jeremy Constantin, Lai Wang, Georgios Karakonstantis, Anupam Chattopadhyay, Andreas Burg:
Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment. DATE 2015: 381-386
2014
[c6]
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  - conf/euc/BraojosBCBA14
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Rubén Braojos, Ivan Beretta, Jeremy Constantin, Andreas Peter Burg, David Atienza:
A Wireless Body Sensor Network for Activity Monitoring with Low Transmission Overhead. EUC 2014: 265-272
2013
[c5]
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  - conf/date/DoganBCABA13
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Ahmed Yasir Dogan, Rubén Braojos, Jeremy Constantin, Giovanni Ansaloni, Andreas Burg, David Atienza:
Synchronizing code execution on ultra-low-power embedded multi-channel signal analysis platforms. DATE 2013: 396-399
2012
[j1]
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  - journals/iet-cds/DoganCABB12
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Ahmed Yasir Dogan, Jeremy Constantin, David Atienza, Andreas Burg, Luca Benini:
Low-power processor architecture exploration for online biomedical signal analysis. IET Circuits, Devices & Systems 6(5): 279-286 (2012)
[c4]
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  - conf/asap/ConstantinBG12
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Jeremy Constantin, Andreas Burg, Frank K. Gürkaynak:
Instruction Set Extensions for Cryptographic Hash Functions on a Microcontroller Architecture. ASAP 2012: 117-124
[c3]
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Ahmed Yasir Dogan, Jeremy Constantin, Martino Ruggiero, Andreas Burg, David Atienza:
Multi-core architecture design for ultra-low-power wearable health monitoring systems. DATE 2012: 988-993
[c2]
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  - conf/vlsi/ConstantinDAMRAB12a
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Jeremy Constantin, Ahmed Yasir Dogan, Oskar Andersson, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues, David Atienza, Andreas Burg:
An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing. VLSI-SoC (Selected Papers) 2012: 88-106
[c1]
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  - conf/vlsi/ConstantinDAMRAB12
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Jeremy Constantin, Ahmed Yasir Dogan, Oskar Andersson, Pascal Andreas Meinerzhagen, Joachim Neves Rodrigues, David Atienza, Andreas Burg:
TamaRISC-CS: An ultra-low-power application-specific processor for compressed sensing. VLSI-SoC 2012: 159-164
[i1]
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Jeremy Constantin, Andreas Burg, Frank K. Gürkaynak:
Investigating the Potential of Custom Instruction Set Extensions for SHA-3 Candidates on a 16-bit Microcontroller Architecture. IACR Cryptology ePrint Archive 2012: 50 (2012)

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