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2010 – 2019
- 2019
[j59]Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides:
Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. ACM Comput. Surv. 52(2): 40:1-40:39 (2019)- [j58]Jianxiong Liu, Christos Bouganis, Peter Y. K. Cheung:
Context-based image acquisition from memory in digital systems. J. Real-Time Image Processing 16(4): 1057-1076 (2019) - [c206]Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides:
LUTNet: Rethinking Inference in FPGA Soft Logic. FCCM 2019: 26-34 - [c205]Qiang Li, Erwei Wang, Shane T. Fleming, David B. Thomas, Peter Y. K. Cheung:
Accelerating Position-Aware Top-k ListNet for Ranking Under Custom Precision Regimes. FPL 2019: 81-87 - [c204]Yiren Zhao, Xitong Gao, Xuan Guo, Junyi Liu, Erwei Wang, Robert D. Mullins, Peter Y. K. Cheung, George A. Constantinides, Cheng-Zhong Xu:
Automatic Generation of Multi-Precision Multi-Arithmetic CNN Accelerators for FPGAs. FPT 2019: 45-53 - [i5]Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides:
Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. CoRR abs/1901.06955 (2019) - [i4]Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides:
LUTNet: Rethinking Inference in FPGA Soft Logic. CoRR abs/1904.00938 (2019) - [i3]Yiren Zhao, Xitong Gao, Xuan Guo, Junyi Liu, Erwei Wang, Robert D. Mullins, Peter Y. K. Cheung, George A. Constantinides, Cheng-Zhong Xu:
Automatic Generation of Multi-precision Multi-arithmetic CNN Accelerators for FPGAs. CoRR abs/1910.10075 (2019) - [i2]Erwei Wang, James J. Davis, Peter Y. K. Cheung, George A. Constantinides:
LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference. CoRR abs/1910.12625 (2019) - 2018
- [j57]Bony H. K. Chen, Paul Y. S. Cheung, Peter Y. K. Cheung, Yu-Kwong Kwok:
CypherDB: A Novel Architecture for Outsourcing Secure Database Processing. IEEE Trans. Cloud Computing 6(2): 372-386 (2018) - [j56]James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs. ACM Trans. Reconfigurable Technol. Syst. 11(1): 2:1-2:22 (2018) - [c203]Jiang Su, Julian Faraone, Junyi Liu, Yiren Zhao, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung:
Redundancy-Reduced MobileNet Acceleration on Reconfigurable Logic for ImageNet Classification. ARC 2018: 16-28 - [c202]Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung:
Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic. ARC 2018: 29-42 - [c201]Ruizhe Zhao, Shuanglong Liu, Ho-Cheung Ng, Erwei Wang, James J. Davis, Xinyu Niu, Xiwei Wang, Huifeng Shi, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Hardware Compilation of Deep Neural Networks: An Overview. ASAP 2018: 1-8 - [c200]Erwei Wang, James J. Davis, Peter Y. K. Cheung:
A PYNQ-Based Framework for Rapid CNN Prototyping. FCCM 2018: 223 - [c199]Qiang Li, Shane T. Fleming, David Thomas, Peter Y. K. Cheung:
Accelerating Top-k ListNet Training for Ranking Using FPGA. FPT 2018: 242-245 - [c198]James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides:
KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications. IWOCL 2018: 4:1 - [i1]Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, Philip Heng Wai Leong, Peter Y. K. Cheung:
Accuracy to Throughput Trade-offs for Reduced Precision Neural Networks on Reconfigurable Logic. CoRR abs/1807.10577 (2018) - 2017
- [j55]James J. Davis
, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides:
KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications. IEEE Des. Test 34(6): 36-45 (2017) - [c197]James J. Davis, Joshua M. Levine, Edward A. Stott, Eddie Hung, Peter Y. K. Cheung, George A. Constantinides:
STRIPE: Signal selection for runtime power estimation. FPL 2017: 1-8 - 2016
- [j54]Jiang Su, Jianxiong Liu, David B. Thomas, Peter Y. K. Cheung:
Neural Network Based Reinforcement Learning Acceleration on FPGA Platforms. SIGARCH Computer Architecture News 44(4): 68-73 (2016) - [c196]James J. Davis, Peter Y. K. Cheung:
Reduced-precision Algorithm-based Fault Tolerance for FPGA-implemented Accelerators. ARC 2016: 361-368 - [c195]Jiang Su, David B. Thomas, Peter Y. K. Cheung:
Increasing Network Size and Training Throughput of FPGA Restricted Boltzmann Machines Using Dropout. FCCM 2016: 48-51 - [c194]Eddie Hung, James J. Davis, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs. FCCM 2016: 56-63 - [c193]James J. Davis, Eddie Hung, Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung, George A. Constantinides:
Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only). FPGA 2016: 276 - 2015
- [j53]Thomas C. P. Chau, Xinyu Niu, Alison Eele, Jan M. Maciejowski, Peter Y. K. Cheung, Wayne Luk:
Mapping Adaptive Particle Filters to Heterogeneous Reconfigurable Systems. ACM Trans. Reconfigurable Technol. Syst. 7(4): 36:1-36:17 (2015) - [c192]Peter Y. K. Cheung, Wayne Luk, Cristina Silvano:
Preface. FPL 2015: 1-2 - [c191]Bony H. K. Chen, Paul Y. S. Cheung, Peter Y. K. Cheung, Yu-Kwong Kwok:
An efficient architecture for zero overhead data en-/decryption using reconfigurable cryptographic engine. FPT 2015: 248-251 - [c190]Andrew Bean, Nachiket Kapre, Peter Y. K. Cheung:
G-DMA: improving memory access performance for hardware accelerated sparse graph computation. ReConFig 2015: 1-6 - 2014
- [j52]Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung:
Classification on variation maps: a new placement strategy to alleviate process variation on FPGA. IEICE Electronic Express 11(3): 20130912 (2014) - [j51]Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung:
Mitigation of process variation effect in FPGAs with partial rerouting method. IEICE Electronic Express 11(3): 20140011 (2014) - [c189]Jianxiong Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung:
Image progressive acquisition for hardware systems. DATE 2014: 1-6 - [c188]Edward A. Stott, Joshua M. Levine, Peter Y. K. Cheung, Nachiket Kapre:
Timing Fault Detection in FPGA-Based Circuits. FCCM 2014: 96-99 - [c187]James J. Davis, Peter Y. K. Cheung:
Reducing Overheads for Fault-Tolerant Datapaths with Dynamic Partial Reconfiguration. FCCM 2014: 103 - [c186]Thomas C. P. Chau, Maciej Kurek, James Stanley Targett, Jake Humphrey, Georgios Skouroupathis, Alison Eele, Jan M. Maciejowski, Benjamin Cope, Kathryn Cobden, Philip Heng Wai Leong, Peter Y. K. Cheung, Wayne Luk:
SMCGen: Generating Reconfigurable Design for Sequential Monte Carlo Applications. FCCM 2014: 141-148 - [c185]Joshua M. Levine, Edward A. Stott, Peter Y. K. Cheung:
Dynamic voltage & frequency scaling with online slack measurement. FPGA 2014: 65-74 - [c184]James J. Davis, Peter Y. K. Cheung:
Achieving low-overhead fault tolerance for parallel accelerators with dynamic partial reconfiguration. FPL 2014: 1-6 - [c183]Jianxiong Liu, Christos Bouganis, Peter Y. K. Cheung:
Kernel-based Adaptive Image Sampling. VISAPP (1) 2014: 25-32 - 2013
- [j50]Edward A. Stott, Zhenyu Guan, Joshua M. Levine, Justin S. J. Wong, Peter Y. K. Cheung:
Variation and Reliability in FPGAs. IEEE Des. Test 30(6): 50-59 (2013) - [j49]Adam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung:
High-level power and performance estimation of FPGA-based soft processors and its application to design space exploration. J. Syst. Archit. 59(10-D): 1144-1156 (2013) - [j48]Thomas C. P. Chau, James Stanley Targett, Marlon Wijeyasinghe, Wayne Luk, Peter Y. K. Cheung, Benjamin Cope, Alison Eele, Jan M. Maciejowski:
Accelerating sequential Monte Carlo method for real-time air traffic management. SIGARCH Computer Architecture News 41(5): 35-40 (2013) - [j47]Justin S. J. Wong, Peter Y. K. Cheung:
Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition Probability. IEEE Trans. Very Large Scale Integr. Syst. 21(12): 2307-2320 (2013) - [c182]Thomas C. P. Chau, Xinyu Niu, Alison Eele, Wayne Luk, Peter Y. K. Cheung, Jan M. Maciejowski:
Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications. ARC 2013: 1-12 - [c181]Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung:
A variation-adaptive retiming method exploiting reconfigurability. FPL 2013: 1-4 - [c180]Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung:
SMI: Slack Measurement Insertion for online timing monitoring in FPGAs. FPL 2013: 1-4 - [c179]Thomas C. P. Chau, Ka-Wai Kwok, Gary C. T. Chow, Kuen Hung Tsoi, Kit-Hang Lee, Zion Tse, Peter Y. K. Cheung, Wayne Luk:
Acceleration of real-time Proximity Query for dynamic active constraints. FPT 2013: 206-213 - [c178]Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung:
Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting. FPT 2013: 254-261 - [c177]James J. Davis, Peter Y. K. Cheung:
Datapath fault tolerance for parallel accelerators. FPT 2013: 366-369 - [c176]Jianxiong Liu, Christos Bouganis, Peter Y. K. Cheung:
Domain-specific progressive sampling of face images. GlobalSIP 2013: 1021-1024 - 2012
- [j46]Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung:
Roberts: reconfigurable platform for benchmarking real-time systems. SIGARCH Computer Architecture News 40(5): 10-15 (2012) - [c175]Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung:
Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling. FCCM 2012: 109-116 - [c174]Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George A. Constantinides, Peter Y. K. Cheung:
A two-stage variation-aware placement method for FPGAS exploiting variation maps classification. FPL 2012: 519-522 - [c173]Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung, Alison Eele, Jan M. Maciejowski:
Adaptive Sequential Monte Carlo approach for real-time applications. FPL 2012: 527-530 - [c172]Adam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung:
Early performance estimation of image compression methods on soft processors. FPL 2012: 587-590 - 2011
- [j45]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organization. Comput. J. 54(1): 1-10 (2011) - [j44]Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung:
Blur identification with assumption validation for sensor-based video reconstruction and its implementation on field programmable gate array. IET Computers & Digital Techniques 5(4): 271-286 (2011) - [j43]Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Howes:
A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors. Trans. High Perform. Embed. Archit. Compil. 4: 63-83 (2011) - [j42]Terrence S. T. Mak, Peter Y. K. Cheung, Kai-Pui Lam, Wayne Luk:
Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network. IEEE Trans. Ind. Electron. 58(8): 3701-3716 (2011) - [j41]Peter Y. K. Cheung:
Introduction to special section FPGA 2009. ACM Trans. Reconfigurable Technol. Syst. 4(4): 31:1 (2011) - [c171]Justin S. J. Wong, Peter Y. K. Cheung:
Improved delay measurement method in FPGA based on transition probability. FPGA 2011: 163-172 - [c170]Joshua M. Levine, Edward A. Stott, George A. Constantinides, Peter Y. K. Cheung:
Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only). FPGA 2011: 284 - [c169]Edward A. Stott, Peter Y. K. Cheung:
Improving FPGA Reliability with Wear-Levelling. FPL 2011: 323-328 - [c168]Sumanta Chaudhuri, Justin S. J. Wong, Peter Y. K. Cheung:
Timing speculation in FPGAs: Probabilistic inference of data dependent failure rates. FPT 2011: 1-8 - 2010
- [j40]Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung:
Fault tolerance and reliability in field-programmable gate arrays. IET Computers & Digital Techniques 4(3): 196-210 (2010) - [j39]Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa:
Power Characterisation for Fine-Grain Reconfigurable Fabrics. Int. J. Reconfigurable Comput. 2010: 787405:1-787405:9 (2010) - [j38]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
Wave-pipelined intra-chip signaling for on-FPGA communications. Integr. 43(2): 188-201 (2010) - [j37]Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Howes:
Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study. IEEE Trans. Computers 59(4): 433-448 (2010) - [j36]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
FPGA Architecture Optimization Using Geometric Programming. IEEE Trans. on CAD of Integrated Circuits and Systems 29(8): 1163-1176 (2010) - [j35]Peter Jamieson, Tobias Becker, Peter Y. K. Cheung, Wayne Luk, Tero Rissa, Teemu Pitkänen:
Benchmarking and evaluating reconfigurable architectures targeting the mobile domain. ACM Trans. Design Autom. Electr. Syst. 15(2): 14:1-14:24 (2010) - [j34]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate Arrays. ACM Trans. Reconfigurable Technol. Syst. 3(3): 13:1-13:21 (2010) - [j33]Asma Kahoul, Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods. ACM Trans. Reconfigurable Technol. Syst. 4(1): 3:1-3:23 (2010) - [j32]Christos-Savvas Bouganis, Iosifina Pournara, Peter Y. K. Cheung:
Exploration of Heterogeneous FPGAs for Mapping Linear Projection Designs. IEEE Trans. Very Large Scale Integr. Syst. 18(3): 436-449 (2010) - [c167]Peter Y. K. Cheung:
Process Variability and Degradation: New Frontier for Reconfigurable. ARC 2010: 2 - [c166]Sebastián López, Roberto Sarmiento, Philip G. Potter, Wayne Luk, Peter Y. K. Cheung:
Exploration of hardware sharing for image encoders. DATE 2010: 1737-1742 - [c165]Tobias Becker, Wayne Luk, Peter Y. K. Cheung:
Energy-Aware Optimisation for Run-Time Reconfiguration. FCCM 2010: 55-62 - [c164]Edward A. Stott, Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung:
Degradation in FPGAs: measurement and modelling. FPGA 2010: 229-238 - [c163]David Huw Jones, Adam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung:
GPU Versus FPGA for High Productivity Computing. FPL 2010: 119-124 - [c162]Edward A. Stott, Justin S. J. Wong, Peter Y. K. Cheung:
Degradation Analysis and Mitigation in FPGAs. FPL 2010: 428-433 - [c161]David Huw Jones, Adam Powell, Christos-Savvas Bouganis, Peter Y. K. Cheung:
A Salient Region Detector for GPU Using a Cellular Automata Architecture. ICONIP (2) 2010: 501-508 - [e4]Peter Y. K. Cheung, John Wawrzynek:
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010. ACM 2010, ISBN 978-1-60558-911-4 [contents]
2000 – 2009
- 2009
- [j31]Yang Liu, Christos-Savvas Bouganis, Peter Y. K. Cheung:
Hardware architectures for eigenvalue computation of real symmetric matrices. IET Computers & Digital Techniques 3(1): 72-84 (2009) - [j30]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems. IET Computers & Digital Techniques 3(3): 235-246 (2009) - [j29]Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk:
High-throughput one-dimensional median and weighted median filters on FPGA. IET Computers & Digital Techniques 3(4): 384-394 (2009) - [j28]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework. IEEE Trans. on CAD of Integrated Circuits and Systems 28(3): 305-315 (2009) - [j27]Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung:
Word-length selection for power minimization via nonlinear optimization. ACM Trans. Design Autom. Electr. Syst. 14(3): 39:1-39:28 (2009) - [j26]Christos-Savvas Bouganis, Sung-Boem Park, George A. Constantinides, Peter Y. K. Cheung:
Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs. ACM Trans. Reconfigurable Technol. Syst. 1(4): 24:1-24:28 (2009) - [j25]Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung:
Self-Measurement of Combinatorial Circuit Delays in FPGAs. ACM Trans. Reconfigurable Technol. Syst. 2(2): 10:1-10:22 (2009) - [j24]Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides:
Robust Real-Time Super-Resolution on FPGA and an Application to Video Enhancement. ACM Trans. Reconfigurable Technol. Syst. 2(4): 22:1-22:29 (2009) - [c160]Tobias Becker, Wayne Luk, Peter Y. K. Cheung:
Parametric Design for Reconfigurable Software-Defined Radio. ARC 2009: 15-26 - [c159]Asma Kahoul, George A. Constantinides, Alastair M. Smith, Peter Y. K. Cheung:
Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep. ARC 2009: 133-144 - [c158]Terrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam:
A DP-network for optimal dynamic routing in network-on-chip. CODES+ISSS 2009: 119-128 - [c157]Philip G. Potter, Wayne Luk, Peter Y. K. Cheung:
Partition-based exploration for reconfigurable JPEG designs. DATE 2009: 886-889 - [c156]Peter Jamieson, Tobias Becker, Wayne Luk, Peter Y. K. Cheung, Tero Rissa, Teemu Pitkänen:
Benchmarking Reconfigurable Architectures in the Mobile Domain. FCCM 2009: 131-138 - [c155]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
Area estimation and optimisation of FPGA routing fabrics. FPL 2009: 256-261 - [c154]N. Pete Sedcole, Edward A. Stott, Peter Y. K. Cheung:
Compensating for variability in FPGAs by re-mapping and re-placement. FPL 2009: 613-616 - [c153]Alastair M. Smith, George A. Constantinides, Steven J. E. Wilton, Peter Y. K. Cheung:
Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design. FPT 2009: 54-61 - [c152]Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung:
A sensor-based approach to linear blur identification for real-time video enhancement. ICIP 2009: 141-144 - [c151]Li Wang, Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung:
Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing. ISCAS 2009: 1293-1296 - [e3]Paul Chow, Peter Y. K. Cheung:
Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009. ACM 2009, ISBN 978-1-60558-410-2 [contents] - 2008
- [j23]Peter Y. K. Cheung, Alexandre Yakovlev:
Comments on the BCS Lecture "The Future of Computer Technology and its Implications for the Computer Industry" by Professor Steve Furber. Comput. J. 51(6): 741-742 (2008) - [j22]Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung:
Custom parallel caching schemes for hardware-accelerated image compression. J. Real-Time Image Processing 3(4): 289-302 (2008) - [j21]Sutjipto Arifin, Peter Y. K. Cheung:
Affective Level Video Segmentation by Utilizing the Pleasure-Arousal-Dominance Information. IEEE Trans. Multimedia 10(7): 1325-1341 (2008) - [j20]N. Pete Sedcole, Peter Y. K. Cheung:
Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations. ACM Trans. Reconfigurable Technol. Syst. 1(2): 10:1-10:28 (2008) - [j19]Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung:
Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices. IEEE Trans. Very Large Scale Integr. Syst. 16(6): 733-744 (2008) - [j18]Kieron Turkington, Turkington A. Constantinides, Kostas Masselos, Peter Y. K. Cheung:
Outer Loop Pipelining for Application Specific Datapaths in FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 16(10): 1268-1280 (2008) - [j17]Maria E. Angelopoulou, Kostas Masselos, Peter Y. K. Cheung, Yiannis Andreopoulos:
Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAs. J. Signal Process. Syst. 51(1): 3-21 (2008) - [c150]Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides:
FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor. ARC 2008: 124-135 - [c149]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation. BCS Int. Acad. Conf. 2008: 295-304 - [c148]Ben Cope, Peter Y. K. Cheung, Wayne Luk:
Using Reconfigurable Logic to Optimise GPU Memory Accesses. DATE 2008: 44-49 - [c147]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
High-throughput interconnect wave-pipelining for global communication in FPGAs. FPGA 2008: 258 - [c146]N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung:
Measuring and modeling FPGA clock variability. FPGA 2008: 258 - [c145]Qiang Liu, George A. Constantinides, Konstantinos Masselos, Peter Y. K. Cheung:
Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework. FPL 2008: 179-184 - [c144]Edward A. Stott, N. Pete Sedcole, Peter Y. K. Cheung:
Fault tolerant methods for reliability in FPGAs. FPL 2008: 415-420 - [c143]Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa:
Towards benchmarking energy efficiency of reconfigurable architectures. FPL 2008: 691-694 - [c142]Justin S. J. Wong, Peter Y. K. Cheung, N. Pete Sedcole:
Combating process variation on FPGAS with a precise at-speed delay measurement method. FPL 2008: 703-704 - [c141]Kieron Turkington, George A. Constantinides, Peter Y. K. Cheung, Konstantinos Masselos:
Co-optimisation of datapath and memory in outer loop pipelining. FPT 2008: 1-8 - [c140]Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk:
Wave-pipelined signaling for on-FPGA communication. FPT 2008: 9-16 - [c139]Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung:
A transition probability based delay measurement method for arbitrary circuits on FPGAs. FPT 2008: 105-112 - [c138]N. Pete Sedcole, Justin S. J. Wong, Peter Y. K. Cheung:
Modelling and compensating for clock skew variability in FPGAs. FPT 2008: 217-224 - [c137]