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Rajarshee P. Bharadwaj

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2000 – 2009

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2006
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Narayan Subramanian, Rajarshee P. Bharadwaj, Dinesh Bhatia:
A leakage aware design methodology for power-gated programmable architectures. FPT 2006: 301-304
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Rajan Konar, Rajarshee P. Bharadwaj, Dinesh Bhatia, Poras T. Balsara:
Exploring Logic Block Granularity in Leakage Tolerant FPGA. VLSI Design 2006: 754-757
2005
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Rajarshee P. Bharadwaj, Rajan Konar, Poras T. Balsara, Dinesh Bhatia:
Exploiting temporal idleness to reduce leakage power in programmable architectures. ASP-DAC 2005: 651-656
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Rajarshee P. Bharadwaj:
Next Generation Architectures and CAD for Power Aware Programmable Fabrics. FPL 2005: 735-738
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Rajarshee P. Bharadwaj, Rajan Konar, Dinesh Bhatia, Poras T. Balsara:
FPGA Architecture for Standby Power Management. FPT 2005: 181-188

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