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Semantic ScholarTor M. Aamodt
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- affiliation: University of Toronto, Canada
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2010 – today
- 2019
[c42]Tayler Hicklin Hetherington, Maria Lubeznov, Deval Shah, Tor M. Aamodt:
EDGE: Event-Driven GPU Execution. PACT 2019: 337-353- [c41]Ayub A. Gubran, Tor M. Aamodt:
Emerald: graphics modeling for SoC systems. ISCA 2019: 169-182 - [c40]Md Aamir Raihan, Negar Goli, Tor M. Aamodt:
Modeling Deep Learning Accelerator Enabled GPUs. ISPASS 2019: 79-92 - [c39]Mahmoud Khairy, Akshay Jain, Tor M. Aamodt, Timothy G. Rogers:
A Detailed Model for Contemporary GPU Memory Systems. ISPASS 2019: 141-142 - [c38]Jonathan Lew, Deval A. Shah, Suchita Pati, Shaylin Cattell, Mengchi Zhang, Amruth Sandhupatla, Christopher Ng, Negar Goli, Matthew D. Sinclair, Timothy G. Rogers, Tor M. Aamodt:
Analyzing Machine Learning Workloads Using a Detailed GPU Simulator. ISPASS 2019: 151-152 - [i8]Ayub A. Gubran, Felix Huang, Tor M. Aamodt:
Surface Compression Using Dynamic Color Palettes. CoRR abs/1903.06658 (2019) - [i7]Francois Demoullin, Ayub A. Gubran, Tor M. Aamodt:
Hash-Based Ray Path Prediction: Skipping BVH Traversal Computation by Exploiting Ray Locality. CoRR abs/1910.01304 (2019) - 2018
- [b1]Tor M. Aamodt, Wilson Wai Lun Fung, Timothy G. Rogers:
General-Purpose Graphics Processor Architectures. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2018 - [j17]Andreas Moshovos, Jorge Albericio, Patrick Judd, Alberto Delmas Lascorz, Sayeh Sharify, Zissis Poulos, Tayler H. Hetherington, Tor M. Aamodt, Natalie D. Enright Jerger:
Exploiting Typical Values to Accelerate Deep Learning. IEEE Computer 51(5): 18-30 (2018) - [j16]Andreas Moshovos, Jorge Albericio, Patrick Judd, Alberto Delmas Lascorz, Sayeh Sharify, Tayler H. Hetherington, Tor M. Aamodt, Natalie D. Enright Jerger:
Value-Based Deep-Learning Acceleration. IEEE Micro 38(1): 41-55 (2018) - [j15]Patrick Judd
, Jorge Albericio, Tayler H. Hetherington, Tor M. Aamodt, Natalie D. Enright Jerger, Raquel Urtasun, Andreas Moshovos:
Proteus: Exploiting precision variability in deep neural networks. Parallel Computing 73: 40-51 (2018) - [c37]Ahmed ElTantawy, Tor M. Aamodt:
Warp Scheduling for Fine-Grained Synchronization. HPCA 2018: 375-388 - [c36]Andreas Moshovos, Jorge Albericio, Patrick Judd, Alberto Delmas, Sayeh Sharify, Mostafa Mahmoud, Tayler H. Hetherington, Milos Nikolic, Dylan Malone Stuart, Kevin Siu, Zissis Poulos, Tor M. Aamodt, Natalie D. Enright Jerger:
Identifying and Exploiting Ineffectual Computations to Enable Hardware Acceleration of Deep Learning. NEWCAS 2018: 356-360 - [i6]Mahmoud Khairy, Akshay Jain, Tor M. Aamodt, Timothy G. Rogers:
Exploring Modern GPU Memory System Design Challenges through Accurate Modeling. CoRR abs/1810.07269 (2018) - [i5]Md Aamir Raihan, Negar Goli, Tor M. Aamodt:
Modeling Deep Learning Accelerator Enabled GPUs. CoRR abs/1811.08309 (2018) - [i4]Jonathan Lew, Deval Shah, Suchita Pati, Shaylin Cattell, Mengchi Zhang, Amruth Sandhupatla, Christopher Ng, Negar Goli, Matthew D. Sinclair, Timothy G. Rogers, Tor M. Aamodt:
Analyzing Machine Learning Workloads Using a Detailed GPU Simulator. CoRR abs/1811.08933 (2018) - 2017
- [j14]Milad Mohammadi, Tor M. Aamodt, William J. Dally:
CG-OoO: Energy-Efficient Coarse-Grain Out-of-Order Execution Near In-Order Energy with Near Out-of-Order Performance. TACO 14(4): 39:1-39:26 (2017) - [c35]Shadi Assadikhomami, Jennifer Ongko, Tor M. Aamodt:
A state machine block for high-level synthesis. ICFPT 2017: 80-87 - [i3]Yatish Turakhia, Subhasis Das, Tor M. Aamodt, William J. Dally:
HoLiSwap: Reducing Wire Energy in L1 Caches. CoRR abs/1701.03878 (2017) - 2016
- [j13]Dongdong Li, Tor M. Aamodt:
Inter-Core Locality Aware Memory Scheduling. Computer Architecture Letters 15(1): 25-28 (2016) - [j12]Subhasis Das, Tor M. Aamodt, William J. Dally:
Reuse Distance-Based Probabilistic Cache Replacement. TACO 12(4): 33:1-33:22 (2016) - [c34]Patrick Judd, Jorge Albericio, Tayler H. Hetherington, Tor M. Aamodt, Natalie D. Enright Jerger, Andreas Moshovos:
Proteus: Exploiting Numerical Precision Variability in Deep Neural Networks. ICS 2016: 23:1-23:12 - [c33]Jorge Albericio, Patrick Judd, Tayler H. Hetherington, Tor M. Aamodt, Natalie D. Enright Jerger, Andreas Moshovos:
Cnvlutin: Ineffectual-Neuron-Free Deep Neural Network Computing. ISCA 2016: 1-13 - [c32]Ahmed ElTantawy, Tor M. Aamodt:
MIMD synchronization on SIMT architectures. MICRO 2016: 11:1-11:14 - [c31]Patrick Judd, Jorge Albericio, Tayler H. Hetherington, Tor M. Aamodt, Andreas Moshovos:
Stripes: Bit-serial deep neural network computing. MICRO 2016: 19:1-19:12 - [i2]Milad Mohammadi, Tor M. Aamodt, William J. Dally:
CG-OoO: Energy-Efficient Coarse-Grain Out-of-Order Execution. CoRR abs/1606.01607 (2016) - 2015
- [j11]Milad Mohammadi, Song Han, Tor M. Aamodt, William J. Dally:
On-Demand Dynamic Branch Prediction. Computer Architecture Letters 14(1): 50-53 (2015) - [c30]Tayler H. Hetherington, Mike O'Connor, Tor M. Aamodt:
MemcachedGPU: scaling-up scale-out key-value stores. SoCC 2015: 43-57 - [c29]Subhasis Das, Tor M. Aamodt, William J. Dally:
SLIP: reducing wire energy in the memory hierarchy. ISCA 2015: 349-361 - [i1]Patrick Judd, Jorge Albericio, Tayler H. Hetherington, Tor M. Aamodt, Natalie D. Enright Jerger, Raquel Urtasun, Andreas Moshovos:
Reduced-Precision Strategies for Bounded Memory in Deep Neural Nets. CoRR abs/1511.05236 (2015) - 2014
- [j10]Timothy G. Rogers, Mike O'Connor, Tor M. Aamodt:
Learning your limit: managing massively multithreaded caches through scheduling. Commun. ACM 57(12): 91-98 (2014) - [j9]Inderpreet Singh, Arrvindh Shriraman, Wilson W. L. Fung, Mike O'Connor, Tor M. Aamodt:
Cache Coherence for GPU Architectures. IEEE Micro 34(3): 69-79 (2014) - [c28]Ahmed ElTantawy, Jessica Wenjie Ma, Mike O'Connor, Tor M. Aamodt:
A scalable multi-path microarchitecture for efficient GPU control flow. HPCA 2014: 248-259 - [c27]Tor M. Aamodt:
Scaling usable computing capability. ICSAMOS 2014: i - 2013
- [j8]Timothy G. Rogers, Mike O'Connor, Tor M. Aamodt:
Cache-Conscious Thread Scheduling for Massively Multithreaded Processors. IEEE Micro 33(3): 78-85 (2013) - [j7]Ali Bakhoda, John Kim, Tor M. Aamodt:
Designing on-chip networks for throughput accelerators. TACO 10(3): 21:1-21:35 (2013) - [c26]Hadi Jooybar, Wilson W. L. Fung, Mike O'Connor, Joseph Devietti, Tor M. Aamodt:
GPUDet: a deterministic GPU architecture. ASPLOS 2013: 1-12 - [c25]Vitaly Zakharenko, Tor M. Aamodt, Andreas Moshovos:
Characterizing the performance benefits of fused CPU/GPU systems using FusionSim. DATE 2013: 685-688 - [c24]Inderpreet Singh, Arrvindh Shriraman, Wilson W. L. Fung, Mike O'Connor, Tor M. Aamodt:
Cache coherence for GPU architectures. HPCA 2013: 578-590 - [c23]Jingwen Leng, Tayler H. Hetherington, Ahmed ElTantawy, Syed Zohaib Gilani, Nam Sung Kim, Tor M. Aamodt, Vijay Janapa Reddi:
GPUWattch: enabling energy optimizations in GPGPUs. ISCA 2013: 487-498 - [c22]Timothy G. Rogers, Mike O'Connor, Tor M. Aamodt:
Divergence-aware warp scheduling. MICRO 2013: 99-110 - [c21]Wilson W. L. Fung, Tor M. Aamodt:
Energy efficient GPU transactional memory via space-time optimizations. MICRO 2013: 408-420 - 2012
- [j6]Wilson Wai Lun Fung, Inderpreet Singh, Andrew Brownsword, Tor M. Aamodt:
Kilo TM: Hardware Transactional Memory for GPU Architectures. IEEE Micro 32(3): 7-16 (2012) - [j5]Xi E. Chen, Tor M. Aamodt:
Modeling Cache Contention and Throughput of Multiprogrammed Manycore Processors. IEEE Trans. Computers 61(7): 913-927 (2012) - [j4]Marcel Gort, Flavio M. de Paula, Johnny J. W. Kuan, Tor M. Aamodt, Alan J. Hu, Steven J. E. Wilton, Jin Yang:
Formal-Analysis-Based Trace Computation for Post-Silicon Debug. IEEE Trans. VLSI Syst. 20(11): 1997-2010 (2012) - [c20]Jimmy Kwa, Tor M. Aamodt:
Small virtual channel routers on FPGAs through block RAM sharing. FPT 2012: 71-79 - [c19]Tayler H. Hetherington, Timothy G. Rogers, Lisa Hsu, Mike O'Connor, Tor M. Aamodt:
Characterizing and evaluating a key-value store application on heterogeneous CPU-GPU systems. ISPASS 2012: 88-98 - [c18]Timothy G. Rogers, Mike O'Connor, Tor M. Aamodt:
Cache-Conscious Wavefront Scheduling. MICRO 2012: 72-83 - [c17]Johnny J. W. Kuan, Tor M. Aamodt:
Progressive-BackSpace: Efficient Predecessor Computation for Post-Silicon Debug. MTV 2012: 70-75 - 2011
- [j3]Xi E. Chen, Tor M. Aamodt:
Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs. TACO 8(3): 10:1-10:28 (2011) - [c16]Wilson W. L. Fung, Tor M. Aamodt:
Thread block compaction for efficient SIMT control flow. HPCA 2011: 25-36 - [c15]Wilson W. L. Fung, Inderpreet Singh, Andrew Brownsword, Tor M. Aamodt:
Hardware transactional memory for GPU architectures. MICRO 2011: 296-307 - 2010
- [c14]Ali Bakhoda, John Kim, Tor M. Aamodt:
On-chip network design considerations for compute accelerators. PACT 2010: 535-536 - [c13]Aaron Ariel, Wilson W. L. Fung, Andrew E. Turner, Tor M. Aamodt:
Visualizing complex dynamics in many-core accelerator architectures. ISPASS 2010: 164-174 - [c12]Johnny J. W. Kuan, Steven J. E. Wilton, Tor M. Aamodt:
Accelerating trace computation in post-silicon debug. ISQED 2010: 244-249 - [c11]Ali Bakhoda, John Kim, Tor M. Aamodt:
Throughput-Effective On-Chip Networks for Manycore Accelerators. MICRO 2010: 421-432
2000 – 2009
- 2009
- [j2]Wilson W. L. Fung, Ivan Sham, George L. Yuan, Tor M. Aamodt:
Dynamic warp formation: Efficient MIMD control flow on SIMD graphics hardware. TACO 6(2): 7:1-7:37 (2009) - [c10]Xi E. Chen, Tor M. Aamodt:
A first-order fine-grained multithreaded throughput model. HPCA 2009: 329-340 - [c9]Ali Bakhoda, George L. Yuan, Wilson W. L. Fung, Henry Wong, Tor M. Aamodt:
Analyzing CUDA workloads using a detailed GPU simulator. ISPASS 2009: 163-174 - [c8]George L. Yuan, Ali Bakhoda, Tor M. Aamodt:
Complexity effective memory access scheduling for many-core accelerator architectures. MICRO 2009: 34-44 - 2008
- [j1]Tor M. Aamodt, Paul Chow:
Compile-time and instruction-set methods for improving floating- to fixed-point conversion accuracy. ACM Trans. Embedded Comput. Syst. 7(3): 26:1-26:27 (2008) - [c7]Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham N. Chinya, Ankur Khandelwal Groen, Hong Jiang, Hong Wang:
Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor. PACT 2008: 52-61 - [c6]Xi E. Chen, Tor M. Aamodt:
Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs. MICRO 2008: 59-70 - 2007
- [c5]Tor M. Aamodt, Paul Chow:
Optimization of data prefetch helper threads with path-expression based statistical modeling. ICS 2007: 210-221 - [c4]Wilson W. L. Fung, Ivan Sham, George L. Yuan, Tor M. Aamodt:
Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow. MICRO 2007: 407-420 - 2004
- [c3]Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wang, John Paul Shen:
Hardware Support for Prescient Instruction Prefetch. HPCA 2004: 84-95 - 2003
- [c2]Tor M. Aamodt, Pedro Marcuello, Paul Chow, Antonio González, Per Hammarlund, Hong Wang, John Paul Shen:
A framework for modeling and optimization of prescient instruction prefetch. SIGMETRICS 2003: 13-24 - 2000
- [c1]Tor M. Aamodt, Paul Chow:
Embedded ISA support for enhanced floating-point to fixed-point ANSI-C compilation. CASES 2000: 128-137
Coauthor Index
aka: Wilson Wai Lun Fung
aka: Tayler Hicklin Hetherington
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