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ORCIDBibTeX records: Ho-Cheung Ng
@article{DBLP:journals/tc/LiuDFKKZNKC24,
author = {Junyi Liu and
Aleksandar Dragojevic and
Shane T. Fleming and
Antonios Katsarakis and
Dario Korolija and
Igor Zablotchi and
Ho{-}Cheung Ng and
Anuj Kalia and
Miguel Castro},
title = {Honeycomb: Ordered Key-Value Store Acceleration on an FPGA-Based SmartNIC},
journal = {{IEEE} Trans. Computers},
volume = {73},
number = {3},
pages = {857--871},
year = {2024}
}
@article{DBLP:journals/corr/abs-2303-14259,
author = {Junyi Liu and
Aleksandar Dragojevic and
Shane Flemming and
Antonios Katsarakis and
Dario Korolija and
Igor Zablotchi and
Ho{-}Cheung Ng and
Anuj Kalia and
Miguel Castro},
title = {Honeycomb: ordered key-value store acceleration on an FPGA-based SmartNIC},
journal = {CoRR},
volume = {abs/2303.14259},
year = {2023}
}
@article{DBLP:journals/tnn/WangLCBNWSTS22,
author = {Maolin Wang and
Kelvin C. M. Lee and
Bob M. F. Chung and
Sharatchandra Varma Bogaraju and
Ho{-}Cheung Ng and
Justin S. J. Wong and
Ho Cheung Shum and
Kevin K. Tsia and
Hayden Kwok{-}Hay So},
title = {Low-Latency In Situ Image Analytics With FPGA-Based Quantized Convolutional
Neural Network},
journal = {{IEEE} Trans. Neural Networks Learn. Syst.},
volume = {33},
number = {7},
pages = {2853--2866},
year = {2022}
}
@inproceedings{DBLP:conf/fpga/NgCLL21,
author = {Ho{-}Cheung Ng and
Izaak Coleman and
Shuanglong Liu and
Wayne Luk},
title = {Reconfigurable Acceleration of Short Read Mapping with Biological
Consideration},
booktitle = {{FPGA}},
pages = {229--239},
publisher = {{ACM}},
year = {2021}
}
@article{DBLP:journals/bmcbi/ColemanCANML20,
author = {Izaak Coleman and
Giacomo Corleone and
James Arram and
Ho{-}Cheung Ng and
Luca Magnani and
Wayne Luk},
title = {GeDi: applying suffix arrays to increase the repertoire of detectable
SNVs in tumour genomes},
journal = {{BMC} Bioinform.},
volume = {21},
number = {1},
pages = {45},
year = {2020}
}
@inproceedings{DBLP:conf/icfpt/NgLCCYL20,
author = {Ho{-}Cheung Ng and
Shuanglong Liu and
Izaak Coleman and
Ringo S. W. Chu and
Man{-}Chung Yue and
Wayne Luk},
title = {Acceleration of Short Read Alignment with Runtime Reconfiguration},
booktitle = {{FPT}},
pages = {256--262},
publisher = {{IEEE}},
year = {2020}
}
@article{DBLP:journals/csur/WangDZNNLCC19,
author = {Erwei Wang and
James J. Davis and
Ruizhe Zhao and
Ho{-}Cheung Ng and
Xinyu Niu and
Wayne Luk and
Peter Y. K. Cheung and
George A. Constantinides},
title = {Deep Neural Network Approximation for Custom Hardware: Where We've
Been, Where We're Going},
journal = {{ACM} Comput. Surv.},
volume = {52},
number = {2},
pages = {40:1--40:39},
year = {2019}
}
@inproceedings{DBLP:conf/asap/MengGNCL19,
author = {Jiuxi Meng and
Nadeen Gebara and
Ho{-}Cheung Ng and
Paolo Costa and
Wayne Luk},
title = {Investigating the Feasibility of FPGA-based Network Switches},
booktitle = {{ASAP}},
pages = {218--226},
publisher = {{IEEE}},
year = {2019}
}
@inproceedings{DBLP:conf/igarss/ChuNWL19,
author = {Ringo S. W. Chu and
Ho{-}Cheung Ng and
Xiwei Wang and
Wayne Luk},
title = {Convolution Based Spectral Partitioning Architecture for Hyperspectral
Image Classification},
booktitle = {{IGARSS}},
pages = {3962--3965},
publisher = {{IEEE}},
year = {2019}
}
@article{DBLP:journals/corr/abs-1901-06955,
author = {Erwei Wang and
James J. Davis and
Ruizhe Zhao and
Ho{-}Cheung Ng and
Xinyu Niu and
Wayne Luk and
Peter Y. K. Cheung and
George A. Constantinides},
title = {Deep Neural Network Approximation for Custom Hardware: Where We've
Been, Where We're Going},
journal = {CoRR},
volume = {abs/1901.06955},
year = {2019}
}
@article{DBLP:journals/corr/abs-1906-11981,
author = {Ringo S. W. Chu and
Ho{-}Cheung Ng and
Xiwei Wang and
Wayne Luk},
title = {Convolution Based Spectral Partitioning Architecture for Hyperspectral
Image Classification},
journal = {CoRR},
volume = {abs/1906.11981},
year = {2019}
}
@article{DBLP:journals/trets/LiuFNNCL18,
author = {Shuanglong Liu and
Hongxiang Fan and
Xinyu Niu and
Ho{-}Cheung Ng and
Yang Chu and
Wayne Luk},
title = {Optimizing CNN-based Segmentation with Deeply Customized Convolutional
and Deconvolutional Architectures on {FPGA}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {3},
pages = {19:1--19:22},
year = {2018}
}
@inproceedings{DBLP:conf/asap/ZhaoLNWDNWSCCL18,
author = {Ruizhe Zhao and
Shuanglong Liu and
Ho{-}Cheung Ng and
Erwei Wang and
James J. Davis and
Xinyu Niu and
Xiwei Wang and
Huifeng Shi and
George A. Constantinides and
Peter Y. K. Cheung and
Wayne Luk},
title = {Hardware Compilation of Deep Neural Networks: An Overview},
booktitle = {{ASAP}},
pages = {1--8},
publisher = {{IEEE} Computer Society},
year = {2018}
}
@inproceedings{DBLP:conf/fpga/NgLL18,
author = {Ho{-}Cheung Ng and
Shuanglong Liu and
Wayne Luk},
title = {{ADAM:} Automated Design Analysis and Merging for Speeding up {FPGA}
Development},
booktitle = {{FPGA}},
pages = {189--198},
publisher = {{ACM}},
year = {2018}
}
@inproceedings{DBLP:conf/fpl/ZhaoNLN18,
author = {Ruizhe Zhao and
Ho{-}Cheung Ng and
Wayne Luk and
Xinyu Niu},
title = {Towards Efficient Convolutional Neural Network for Domain-Specific
Applications on {FPGA}},
booktitle = {{FPL}},
pages = {147--154},
publisher = {{IEEE} Computer Society},
year = {2018}
}
@inproceedings{DBLP:conf/fpl/FanNLQNL18,
author = {Hongxiang Fan and
Ho{-}Cheung Ng and
Shuanglong Liu and
Zhiqiang Que and
Xinyu Niu and
Wayne Luk},
title = {Reconfigurable Acceleration of 3D-CNNs for Human Action Recognition
with Block Floating-Point Representation},
booktitle = {{FPL}},
pages = {287--294},
publisher = {{IEEE} Computer Society},
year = {2018}
}
@inproceedings{DBLP:conf/fpt/FanLFNQLNL18,
author = {Hongxiang Fan and
Shuanglong Liu and
Martin Ferianc and
Ho{-}Cheung Ng and
Zhiqiang Que and
Shen Liu and
Xinyu Niu and
Wayne Luk},
title = {A Real-Time Object Detection Accelerator with Compressed SSDLite on
{FPGA}},
booktitle = {{FPT}},
pages = {14--21},
publisher = {{IEEE}},
year = {2018}
}
@inproceedings{DBLP:conf/fpt/LiuZFNMQNL18,
author = {Shuanglong Liu and
Chenglong Zeng and
Hongxiang Fan and
Ho{-}Cheung Ng and
Jiuxi Meng and
Zhiqiang Que and
Xinyu Niu and
Wayne Luk},
title = {Memory-Efficient Architecture for Accelerating Generative Networks
on {FPGA}},
booktitle = {{FPT}},
pages = {30--37},
publisher = {{IEEE}},
year = {2018}
}
@article{DBLP:journals/corr/abs-1809-03318,
author = {Ruizhe Zhao and
Ho{-}Cheung Ng and
Wayne Luk and
Xinyu Niu},
title = {Towards Efficient Convolutional Neural Network for Domain-Specific
Applications on {FPGA}},
journal = {CoRR},
volume = {abs/1809.03318},
year = {2018}
}
@inproceedings{DBLP:conf/fccm/HoHNWS17,
author = {Sam M. H. Ho and
C.{-}H. Dominic Hung and
Ho{-}Cheung Ng and
Maolin Wang and
Hayden Kwok{-}Hay So},
title = {A Parameterizable Activation Function Generator for FPGA-Based Neural
Network Applications},
booktitle = {{FCCM}},
pages = {84},
publisher = {{IEEE} Computer Society},
year = {2017}
}
@inproceedings{DBLP:conf/fpl/NgLL17,
author = {Ho{-}Cheung Ng and
Shuanglong Liu and
Wayne Luk},
title = {Reconfigurable acceleration of genetic sequence alignment: {A} survey
of two decades of efforts},
booktitle = {{FPL}},
pages = {1--8},
publisher = {{IEEE}},
year = {2017}
}
@inproceedings{DBLP:conf/fpt/WangNCVJTSS16,
author = {Maolin Wang and
Ho{-}Cheung Ng and
Bob M. F. Chung and
B. Sharat Chandra Varma and
Manish Kumar Jaiswal and
Kevin K. Tsia and
Ho Cheung Shum and
Hayden Kwok{-}Hay So},
title = {Real-time object detection and classification for high-speed asymmetric-detection
time-stretch optical microscopy on {FPGA}},
booktitle = {{FPT}},
pages = {261--264},
publisher = {{IEEE}},
year = {2016}
}
@inproceedings{DBLP:conf/reconfig/HoWNS16,
author = {Sam M. H. Ho and
Maolin Wang and
Ho{-}Cheung Ng and
Hayden Kwok{-}Hay So},
title = {Towards FPGA-assisted spark: An {SVM} training acceleration case study},
booktitle = {ReConFig},
pages = {1--6},
publisher = {{IEEE}},
year = {2016}
}
@inproceedings{DBLP:conf/reconfig/NgWCVJHTSS16,
author = {Ho{-}Cheung Ng and
Maolin Wang and
Bob M. F. Chung and
B. Sharat Chandra Varma and
Manish Kumar Jaiswal and
Sam M. H. Ho and
Kevin K. Tsia and
Ho Cheung Shum and
Hayden Kwok{-}Hay So},
title = {High-throughput cellular imaging with high-speed asymmetric-detection
time-stretch optical microscopy under {FPGA} platform},
booktitle = {ReConFig},
pages = {1--6},
publisher = {{IEEE}},
year = {2016}
}
@article{DBLP:journals/corr/NgLS16,
author = {Ho{-}Cheung Ng and
Cheng Liu and
Hayden Kwok{-}Hay So},
title = {A Soft Processor Overlay with Tightly-coupled {FPGA} Accelerator},
journal = {CoRR},
volume = {abs/1606.06483},
year = {2016}
}
@phdthesis{DBLP:phd/basesearch/Ng15,
author = {Ho{-}Cheung Ng},
title = {A soft processor overlay with tightly-coupled {FPGA} accelerator},
school = {University of Hong Kong, Pokfulam, Hong Kong},
year = {2015}
}
@inproceedings{DBLP:conf/fpt/LiuNS15,
author = {Cheng Liu and
Ho{-}Cheung Ng and
Hayden Kwok{-}Hay So},
title = {QuickDough: {A} rapid {FPGA} loop accelerator design framework using
soft {CGRA} overlay},
booktitle = {{FPT}},
pages = {56--63},
publisher = {{IEEE}},
year = {2015}
}
@article{DBLP:journals/corr/LiuNS15,
author = {Cheng Liu and
Ho{-}Cheung Ng and
Hayden Kwok{-}Hay So},
title = {Automatic Nested Loop Acceleration on FPGAs Using Soft {CGRA} Overlay},
journal = {CoRR},
volume = {abs/1509.00042},
year = {2015}
}
@inproceedings{DBLP:conf/nime/DengLNKCL14,
author = {Jun{-}qi Deng and
Francis Chi{-}Moon Lau and
Ho{-}Cheung Ng and
Yu{-}Kwong Kwok and
Hung{-}Kwan Chen and
Yuheng Liu},
title = {{WIJAM:} {A} Mobile Collaborative Improvisation Platform under Master-players
Paradigm},
booktitle = {{NIME}},
pages = {407--410},
publisher = {nime.org},
year = {2014}
}
@inproceedings{DBLP:conf/fpt/NgCS13,
author = {Ho{-}Cheung Ng and
Yuk{-}Ming Choi and
Hayden Kwok{-}Hay So},
title = {Direct virtual memory access from {FPGA} for high-productivity heterogeneous
computing},
booktitle = {{FPT}},
pages = {458--461},
publisher = {{IEEE}},
year = {2013}
}
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