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ORCIDBibTeX records: M. B. Srinivas
@inproceedings{DBLP:conf/aicas/ChandraGSS24,
author = {Harshiv Chandra and
Akash Ghosh and
Rahul Singh and
M. B. Srinivas},
title = {{SNN-LIF} Model for Glaucoma Classification},
booktitle = {6th {IEEE} International Conference on {AI} Circuits and Systems,
{AICAS} 2024, Abu Dhabi, United Arab Emirates, April 22-25, 2024},
pages = {114--118},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/AICAS59952.2024.10595951},
doi = {10.1109/AICAS59952.2024.10595951},
timestamp = {Wed, 31 Jul 2024 16:24:36 +0200},
biburl = {https://dblp.org/rec/conf/aicas/ChandraGSS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jaihc/GuptaSYSC23,
author = {Khushi Gupta and
Arshdeep Singh and
Sreenivasa Reddy Yeduri and
M. B. Srinivas and
Linga Reddy Cenkeramaddi},
title = {Hand gestures recognition using edge computing system based on vision
transformer and lightweight {CNN}},
journal = {J. Ambient Intell. Humaniz. Comput.},
volume = {14},
number = {3},
pages = {2601--2615},
year = {2023},
url = {https://doi.org/10.1007/s12652-022-04506-4},
doi = {10.1007/S12652-022-04506-4},
timestamp = {Sat, 11 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jaihc/GuptaSYSC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jpdc/ChinnakkondaRS22,
author = {Diyanesh Chinnakkonda and
Karthick Rajamani and
M. B. Srinivas},
title = {Architecture slack exploitation for phase classification and performance
estimation in server-class processors},
journal = {J. Parallel Distributed Comput.},
volume = {169},
pages = {157--170},
year = {2022},
url = {https://doi.org/10.1016/j.jpdc.2022.06.017},
doi = {10.1016/J.JPDC.2022.06.017},
timestamp = {Thu, 22 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jpdc/ChinnakkondaRS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sncs/PhaneendraVS22,
author = {P. Sai Phaneendra and
Chetan Vudadha and
M. B. Srinivas},
title = {Optimization of Reversible Circuits Using Gate Pair Classification},
journal = {{SN} Comput. Sci.},
volume = {3},
number = {1},
pages = {40},
year = {2022},
url = {https://doi.org/10.1007/s42979-021-00900-5},
doi = {10.1007/S42979-021-00900-5},
timestamp = {Mon, 08 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/sncs/PhaneendraVS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SethuramanTS22,
author = {Saravanan Sethuraman and
Venkata Kalyan Tavva and
M. B. Srinivas},
title = {Techniques to Improve Write and Retention Reliability of {STT-MRAM}
Memory Subsystem},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {9},
pages = {2901--2914},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2021.3118210},
doi = {10.1109/TCAD.2021.3118210},
timestamp = {Sat, 10 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SethuramanTS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AdimulamS22,
author = {Mahesh Kumar Adimulam and
M. B. Srinivas},
title = {A 12-bit, 1.1-GS/s, Low-Power Flash {ADC}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {3},
pages = {277--290},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2021.3138538},
doi = {10.1109/TVLSI.2021.3138538},
timestamp = {Fri, 01 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AdimulamS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cem/ThapliyalMMSG21,
author = {Himanshu Thapliyal and
Katina Michael and
Saraju P. Mohanty and
M. B. Srinivas and
Madhavi K. Ganapathiraju},
title = {Consumer Technology-Based Solutions for {COVID-19}},
journal = {{IEEE} Consumer Electron. Mag.},
volume = {10},
number = {2},
pages = {64--65},
year = {2021},
url = {https://doi.org/10.1109/MCE.2020.3040513},
doi = {10.1109/MCE.2020.3040513},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/cem/ThapliyalMMSG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/comsnets/BhatiaDJVJSYKLK21,
author = {Jyoti Bhatia and
Aveen Dayal and
Ajit Jha and
Santosh Kumar Vishvakarma and
Soumya J. and
M. B. Srinivas and
Phaneendra K. Yalavarthy and
Abhinav Kumar and
V. Lalitha and
Sagar Koorapati and
Linga Reddy Cenkeramaddi},
title = {Object Classification Technique for mmWave {FMCW} Radars using Range-FFT
Features},
booktitle = {13th International Conference on COMmunication Systems {\&} NETworkS,
{COMSNETS} 2021, Bangalore, India, January 5-9, 2021},
pages = {111--115},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/COMSNETS51098.2021.9352894},
doi = {10.1109/COMSNETS51098.2021.9352894},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/comsnets/BhatiaDJVJSYKLK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ner/SaiTejaKCJAS21,
author = {Kotturi Venkata SaiTeja and
Ponduru Manoj Kumar and
Punnamraju Sarath Chandra and
N. K. Jisy and
Md. Hasnat Ali and
M. B. Srinivas},
title = {'Glaucoma - Automating the Cup-to-Disc Ratio Estimation in Fundus
Images by Combining Random Walk Algorithm with Otsu Thresholding'},
booktitle = {10th International {IEEE/EMBS} Conference on Neural Engineering, {NER}
2021, Virtual Event, Italy, May 4-6, 2021},
pages = {154--157},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/NER49283.2021.9441435},
doi = {10.1109/NER49283.2021.9441435},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ner/SaiTejaKCJAS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SethuramanTRSKH20,
author = {Saravanan Sethuraman and
Venkata Kalyan Tavva and
Karthick Rajamani and
Chitra K. Subramanian and
Kyu{-}Hyoun Kim and
Hillery C. Hunter and
M. B. Srinivas},
title = {Temperature Aware Adaptations for Improved Read Reliability in {STT-MRAM}
Memory Subsystem},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {39},
number = {12},
pages = {4635--4644},
year = {2020},
url = {https://doi.org/10.1109/TCAD.2020.2982134},
doi = {10.1109/TCAD.2020.2982134},
timestamp = {Fri, 28 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SethuramanTRSKH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tii/VulligaddalaVSA20,
author = {Veeresh Babu Vulligaddala and
Sandeep Vernekar and
Sudhakar Singamala and
Ravi Kumar Adusumalli and
Vijay Ele and
Manfred Brandl and
M. B. Srinivas},
title = {A 7-Cell, Stackable, Li-Ion Monitoring and Active/Passive Balancing
{IC} With In-Built Cell Balancing Switches for Electric and Hybrid
Vehicles},
journal = {{IEEE} Trans. Ind. Informatics},
volume = {16},
number = {5},
pages = {3335--3344},
year = {2020},
url = {https://doi.org/10.1109/TII.2019.2953939},
doi = {10.1109/TII.2019.2953939},
timestamp = {Tue, 09 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tii/VulligaddalaVSA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cssp/MakkenaS19,
author = {Goutham Makkena and
M. B. Srinivas},
title = {Levin's Transformation-based Continuous-Time Linear-Phase Selective
Filters},
journal = {Circuits Syst. Signal Process.},
volume = {38},
number = {11},
pages = {4905--4920},
year = {2019},
url = {https://doi.org/10.1007/s00034-019-01105-1},
doi = {10.1007/S00034-019-01105-1},
timestamp = {Sun, 21 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/cssp/MakkenaS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sivp/VaidyaS19,
author = {Avinash S. Vaidya and
M. B. Srinivas},
title = {A frequency domain beamspace adaptive receive beamformer for ultrasound
imaging systems: phantom simulation results},
journal = {Signal Image Video Process.},
volume = {13},
number = {3},
pages = {591--599},
year = {2019},
url = {https://doi.org/10.1007/s11760-018-1386-6},
doi = {10.1007/S11760-018-1386-6},
timestamp = {Sun, 06 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sivp/VaidyaS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsisp/AhmedS19,
author = {Syed Ershad Ahmed and
M. B. Srinivas},
title = {An Improved Logarithmic Multiplier for Media Processing},
journal = {J. Signal Process. Syst.},
volume = {91},
number = {6},
pages = {561--574},
year = {2019},
url = {https://doi.org/10.1007/s11265-018-1350-2},
doi = {10.1007/S11265-018-1350-2},
timestamp = {Thu, 12 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/vlsisp/AhmedS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cssp/MakkenaS18,
author = {Goutham Makkena and
M. B. Srinivas},
title = {Nonlinear Sequence Transformation-Based Continuous-Time Wavelet Filter
Approximation},
journal = {Circuits Syst. Signal Process.},
volume = {37},
number = {3},
pages = {965--983},
year = {2018},
url = {https://doi.org/10.1007/s00034-017-0591-9},
doi = {10.1007/S00034-017-0591-9},
timestamp = {Sun, 21 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/cssp/MakkenaS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/AhmedVS18,
author = {Syed Ershad Ahmed and
Ch. Santosh Varma and
M. B. Srinivas},
title = {Improved designs of digit-by-digit decimal multiplier},
journal = {Integr.},
volume = {61},
pages = {150--159},
year = {2018},
url = {https://doi.org/10.1016/j.vlsi.2017.12.001},
doi = {10.1016/J.VLSI.2017.12.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/AhmedVS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/VulligaddalaASS18,
author = {Veeresh Babu Vulligaddala and
Ravikumar Adusumalli and
Sudhakar Singamala and
M. B. Srinivas},
title = {A Digitally Calibrated Bandgap Reference With 0.06{\%} Error for Low-Side
Current Sensing Application},
journal = {{IEEE} J. Solid State Circuits},
volume = {53},
number = {10},
pages = {2951--2957},
year = {2018},
url = {https://doi.org/10.1109/JSSC.2018.2859984},
doi = {10.1109/JSSC.2018.2859984},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/VulligaddalaASS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/VudadhaPS18,
author = {Chetan Vudadha and
Sai Phaneendra Parlapalli and
M. B. Srinivas},
title = {Energy efficient design of CNFET-based multi-digit ternary adders},
journal = {Microelectron. J.},
volume = {75},
pages = {75--86},
year = {2018},
url = {https://doi.org/10.1016/j.mejo.2018.02.004},
doi = {10.1016/J.MEJO.2018.02.004},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/VudadhaPS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/VudadhaSAS18,
author = {Chetan Vudadha and
Ajay Surya and
Saurabh Agrawal and
M. B. Srinivas},
title = {Synthesis of Ternary Logic Circuits Using 2: 1 Multiplexers},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {65-I},
number = {12},
pages = {4313--4325},
year = {2018},
url = {https://doi.org/10.1109/TCSI.2018.2838258},
doi = {10.1109/TCSI.2018.2838258},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/VudadhaSAS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/CenkeramaddiGBB18,
author = {Linga Reddy Cenkeramaddi and
Ashish Goyal and
Asheesh Bhuria and
M. B. Srinivas and
Soumya J.},
title = {Design of Software and Data Analytics for Self-Powered Wireless IoT
Devices},
booktitle = {{IEEE} International Symposium on Smart Electronic Systems, iSES 2018
(Formerly iNiS), Hyderabad, India, December 17-19, 2018},
pages = {118--123},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/iSES.2018.00034},
doi = {10.1109/ISES.2018.00034},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ises/CenkeramaddiGBB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/VudadhaS18,
author = {Chetan Vudadha and
M. B. Srinivas},
title = {Design Methodologies for Ternary Logic Circuits},
booktitle = {48th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2018, Linz, Austria, May 16-18, 2018},
pages = {192--197},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/ISMVL.2018.00041},
doi = {10.1109/ISMVL.2018.00041},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/VudadhaS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/AdimulamKVS18,
author = {Mahesh Kumar Adimulam and
Amit Kapoor and
Sreehari Veeramachaneni and
M. B. Srinivas},
title = {An Ultra Low Power, 10-Bit Two-Step Flash {ADC} for Signal Processing
Applications},
booktitle = {31st International Conference on {VLSI} Design and 17th International
Conference on Embedded Systems, {VLSID} 2018, Pune, India, January
6-10, 2018},
pages = {19--24},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/VLSID.2018.31},
doi = {10.1109/VLSID.2018.31},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/AdimulamKVS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/embc/AdimulamDTS17,
author = {Mahesh Kumar Adimulam and
Adimulam Divya and
K. Tejaswi and
M. B. Srinivas},
title = {A low power, low noise Programmable Analog Front End {(PAFE)} for
biopotential measurements},
booktitle = {2017 39th Annual International Conference of the {IEEE} Engineering
in Medicine and Biology Society (EMBC), Jeju Island, South Korea,
July 11-15, 2017},
pages = {3844--3847},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/EMBC.2017.8037695},
doi = {10.1109/EMBC.2017.8037695},
timestamp = {Wed, 16 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/embc/AdimulamDTS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/AdimulamMKS17,
author = {Mahesh Kumar Adimulam and
Krishna Kumar Movva and
K. Kolluru and
M. B. Srinivas},
title = {A 0.32 {\(\mathrm{\mu}\)}W, 76.8 dB {SNDR} Programmable Gain Instrumentation
Amplifier for Bio-Potential Signal Processing Applications},
booktitle = {2017 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2017,
Bochum, Germany, July 3-5, 2017},
pages = {655--660},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ISVLSI.2017.119},
doi = {10.1109/ISVLSI.2017.119},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/AdimulamMKS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mobihealth/AdimulamS17,
author = {Mahesh Kumar Adimulam and
M. B. Srinivas},
editor = {Paolo Perego and
Amir M. Rahmani and
Nima Taherinejad},
title = {Ultra Low Power Programmable Wireless ExG SoC Design for IoT Healthcare
System},
booktitle = {Wireless Mobile Communication and Healthcare - 7th International Conference,
MobiHealth 2017, Vienna, Austria, November 14-15, 2017, Proceedings},
series = {Lecture Notes of the Institute for Computer Sciences, Social Informatics
and Telecommunications Engineering},
volume = {247},
pages = {41--49},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-319-98551-0\_5},
doi = {10.1007/978-3-319-98551-0\_5},
timestamp = {Sat, 01 Sep 2018 12:23:57 +0200},
biburl = {https://dblp.org/rec/conf/mobihealth/AdimulamS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rc/ParlapalliVS17,
author = {Sai Phaneendra Parlapalli and
Chetan Vudadha and
M. B. Srinivas},
editor = {Iain Phillips and
Hafizur Rahaman},
title = {Optimizing the Reversible Circuits Using Complementary Control Line
Transformation},
booktitle = {Reversible Computation - 9th International Conference, {RC} 2017,
Kolkata, India, July 6-7, 2017, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {10301},
pages = {111--126},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-319-59936-6\_9},
doi = {10.1007/978-3-319-59936-6\_9},
timestamp = {Tue, 22 Oct 2019 15:21:14 +0200},
biburl = {https://dblp.org/rec/conf/rc/ParlapalliVS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rc/ParlapalliVS17a,
author = {Sai Phaneendra Parlapalli and
Chetan Vudadha and
M. B. Srinivas},
editor = {Iain Phillips and
Hafizur Rahaman},
title = {An {ESOP} Based Cube Decomposition Technique for Reversible Circuits},
booktitle = {Reversible Computation - 9th International Conference, {RC} 2017,
Kolkata, India, July 6-7, 2017, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {10301},
pages = {127--140},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-3-319-59936-6\_10},
doi = {10.1007/978-3-319-59936-6\_10},
timestamp = {Mon, 26 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/rc/ParlapalliVS17a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/Srinivas17,
author = {M. B. Srinivas},
editor = {Massimo Alioto and
Hai Helen Li and
J{\"{u}}rgen Becker and
Ulf Schlichtmann and
Ramalingam Sridhar},
title = {{T2A:} Analog and {RF} circuits},
booktitle = {30th {IEEE} International System-on-Chip Conference, {SOCC} 2017,
Munich, Germany, September 5-8, 2017},
pages = {1},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/SOCC.2017.8226050},
doi = {10.1109/SOCC.2017.8226050},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/socc/Srinivas17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/AdimulamMS17,
author = {Mahesh Kumar Adimulam and
Krishna Kumar Movva and
M. B. Srinivas},
editor = {Massimo Alioto and
Hai Helen Li and
J{\"{u}}rgen Becker and
Ulf Schlichtmann and
Ramalingam Sridhar},
title = {A low power, programmable 12-bit two step SAR-flash {ADC} for signal
processing applications},
booktitle = {30th {IEEE} International System-on-Chip Conference, {SOCC} 2017,
Munich, Germany, September 5-8, 2017},
pages = {45--50},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/SOCC.2017.8226004},
doi = {10.1109/SOCC.2017.8226004},
timestamp = {Fri, 22 Dec 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/socc/AdimulamMS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AdimulamMKS17,
author = {Mahesh Kumar Adimulam and
Krishna Kumar Movva and
Amit Kapoor and
M. B. Srinivas},
title = {A low power, programmable bias inverter quantizer {(BIQ)} flash {ADC}},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203489},
doi = {10.1109/VLSI-SOC.2017.8203489},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AdimulamMKS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/GopinathAVS17,
author = {Anjali Gopinath and
Ravi Kumar Adusumalli and
Veeresh Babu Vulligaddala and
M. B. Srinivas},
title = {A Switched-Capacitor Amplifier with True Rail-to-Rail Input Range
without Using a Rail-to-Rail Op-Amp},
booktitle = {30th International Conference on {VLSI} Design and 16th International
Conference on Embedded Systems, {VLSID} 2017, Hyderabad, India, January
7-11, 2017},
pages = {329--334},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/VLSID.2017.31},
doi = {10.1109/VLSID.2017.31},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/GopinathAVS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijbdcn/RakheeS16,
author = {Rakhee and
M. B. Srinivas},
title = {A Soft Computing Approach for Data Routing in Hospital Area Networks
{(HAN)}},
journal = {Int. J. Bus. Data Commun. Netw.},
volume = {12},
number = {2},
pages = {16--27},
year = {2016},
url = {https://doi.org/10.4018/IJBDCN.2016070102},
doi = {10.4018/IJBDCN.2016070102},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ijbdcn/RakheeS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arith/AhmedKS16,
author = {Syed Ershad Ahmed and
Sanket Kadam and
M. B. Srinivas},
editor = {Paolo Montuschi and
Michael J. Schulte and
Javier Hormigo and
Stuart F. Oberman and
Nathalie Revol},
title = {An Iterative Logarithmic Multiplier with Improved Precision},
booktitle = {23nd {IEEE} Symposium on Computer Arithmetic, {ARITH} 2016, Silicon
Valley, CA, USA, July 10-13, 2016},
pages = {104--111},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ARITH.2016.25},
doi = {10.1109/ARITH.2016.25},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/arith/AhmedKS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/bmei/AdimulamS16,
author = {Mahesh Kumar Adimulam and
M. B. Srinivas},
editor = {Yaoli Wang and
Jiancheng An and
Lipo Wang and
Qingli Li and
Gaowei Van and
Qing Chang},
title = {Modeling of {EXG} (ECG, {EMG} and {EEG)} non-idealities using {MATLAB}},
booktitle = {9th International Congress on Image and Signal Processing, BioMedical
Engineering and Informatics, {CISP-BMEI} 2016, Datong, China, October
15-17, 2016},
pages = {1584--1589},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/CISP-BMEI.2016.7852968},
doi = {10.1109/CISP-BMEI.2016.7852968},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/bmei/AdimulamS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ises/VudadhaPS16,
author = {Chetan Vudadha and
P. Sai Phaneendra and
M. B. Srinivas},
title = {An Efficient Design Methodology for {CNFET} Based Ternary Logic Circuits},
booktitle = {{IEEE} International Symposium on Nanoelectronic and Information Systems,
iNIS 2016, Gwalior, India, December 19-21, 2016},
pages = {278--283},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/iNIS.2016.070},
doi = {10.1109/INIS.2016.070},
timestamp = {Mon, 08 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ises/VudadhaPS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/AhmedSS16,
author = {Syed Ershad Ahmed and
S. Sweekruth Srinivas and
M. B. Srinivas},
title = {A Hybrid Energy Efficient Digital Comparator},
booktitle = {29th International Conference on {VLSI} Design and 15th International
Conference on Embedded Systems, {VLSID} 2016, Kolkata, India, January
4-8, 2016},
pages = {567--568},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/VLSID.2016.114},
doi = {10.1109/VLSID.2016.114},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/AhmedSS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/GangulyMAS14,
author = {Soumya Ganguly and
Abhishek Mittal and
Syed Ershad Ahmed and
M. B. Srinivas},
title = {A unified flagged prefix constant addition-subtraction scheme for
design of area and power efficient binary floating-point and constant
integer arithmetic circuits},
booktitle = {2014 {IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS}
2014, Ishigaki, Japan, November 17-20, 2014},
pages = {69--72},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/APCCAS.2014.7032721},
doi = {10.1109/APCCAS.2014.7032721},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/apccas/GangulyMAS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/biostec/VaidyaRSM14,
author = {Avinash S. Vaidya and
T. S. L. Radhika and
M. B. Srinivas and
Mannan Mridha},
editor = {Alberto Cliquet Junior and
Guy Plantier and
Tanja Schultz and
Ana L. N. Fred and
Hugo Gamboa},
title = {Estimation of Arterial Stiffness through Pulse Transit Time Measurement},
booktitle = {{BIODEVICES} 2014 - Proceedings of the International Conference on
Biomedical Electronics and Devices, ESEO, Angers, Loire Valley, France,
3-6 March, 2014},
pages = {238--242},
publisher = {SciTePress},
year = {2014},
url = {https://doi.org/10.5220/0004912002380242},
doi = {10.5220/0004912002380242},
timestamp = {Mon, 01 Apr 2024 00:12:16 +0200},
biburl = {https://dblp.org/rec/conf/biostec/VaidyaRSM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ised/PalVPVM14,
author = {Subhankar Pal and
Chetan Vudadha and
P. Sai Phaneendra and
Sreehari Veeramachaneni and
Srinivas B. Mandalika},
title = {A New Design of an N-Bit Reversible Arithmetic Logic Unit},
booktitle = {2014 Fifth International Symposium on Electronic System Design, Surathkal,
Mangalore, India, December 15-17, 2014},
pages = {224--225},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/ISED.2014.56},
doi = {10.1109/ISED.2014.56},
timestamp = {Mon, 08 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ised/PalVPVM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/NS14,
author = {Abhilash K. N and
M. B. Srinivas},
editor = {Kaijian Shi and
Thomas B{\"{u}}chner and
Danella Zhao and
Ramalingam Sridhar},
title = {A reconfigurable 0-L1-L2 S-MASH\({}^{\mbox{2}}\) modulator with high-level
sizing and power estimation},
booktitle = {27th {IEEE} International System-on-Chip Conference, {SOCC} 2014,
Las Vegas, NV, USA, September 2-5, 2014},
pages = {347--352},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/SOCC.2014.6948952},
doi = {10.1109/SOCC.2014.6948952},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/socc/NS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/ReddySVS14,
author = {B. Naveen Kumar Reddy and
M. Chandra Sekhar and
Sreehari Veeramachaneni and
M. B. Srinivas},
title = {A Novel Low Power Error Detection Logic for Inexact Leading Zero Anticipator
in Floating Point Units},
booktitle = {2014 27th International Conference on {VLSI} Design, {VLSID} 2014,
and 2014 13th International Conference on Embedded Systems, Mumbai,
India, January 5-9, 2014},
pages = {128--132},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/VLSID.2014.29},
doi = {10.1109/VLSID.2014.29},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/ReddySVS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/VarmaAS14,
author = {Ch. Santosh Varma and
Syed Ershad Ahmed and
M. B. Srinivas},
title = {A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal
Converter},
booktitle = {2014 27th International Conference on {VLSI} Design, {VLSID} 2014,
and 2014 13th International Conference on Embedded Systems, Mumbai,
India, January 5-9, 2014},
pages = {365--368},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/VLSID.2014.69},
doi = {10.1109/VLSID.2014.69},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/VarmaAS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PVVS14,
author = {P. Sai Phaneendra and
Chetan Vudadha and
Sreehari Veeramachaneni and
M. B. Srinivas},
title = {An Optimized Design of Reversible Quantum Comparator},
booktitle = {2014 27th International Conference on {VLSI} Design, {VLSID} 2014,
and 2014 13th International Conference on Embedded Systems, Mumbai,
India, January 5-9, 2014},
pages = {557--562},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/VLSID.2014.103},
doi = {10.1109/VLSID.2014.103},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PVVS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/embc/MakkenaRS13,
author = {Goutham Makkena and
Prabhakara Rao and
M. B. Srinivas},
title = {Uniform approximation of Gaussian wavelet for biomedical signal processing
in analog domain},
booktitle = {35th Annual International Conference of the {IEEE} Engineering in
Medicine and Biology Society, {EMBC} 2013, Osaka, Japan, July 3-7,
2013},
pages = {2886--2889},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/EMBC.2013.6610143},
doi = {10.1109/EMBC.2013.6610143},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/embc/MakkenaRS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/embc/VaidyaSHJ13,
author = {Avinash S. Vaidya and
M. B. Srinivas and
P. Himabindu and
Daria Jumaxanova},
title = {A smart phone/tablet based mobile health care system for developing
countries},
booktitle = {35th Annual International Conference of the {IEEE} Engineering in
Medicine and Biology Society, {EMBC} 2013, Osaka, Japan, July 3-7,
2013},
pages = {4642--4645},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/EMBC.2013.6610582},
doi = {10.1109/EMBC.2013.6610582},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/embc/VaidyaSHJ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cyberc/JenaS12,
author = {Santosh Kumar Jena and
M. B. Srinivas},
title = {On the Suitability of Multi-Core Processing for Embedded Automotive
Systems},
booktitle = {2012 International Conference on Cyber-Enabled Distributed Computing
and Knowledge Discovery, CyberC 2012, Sanya, China, October 10-12,
2012},
pages = {315--322},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/CyberC.2012.60},
doi = {10.1109/CYBERC.2012.60},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cyberc/JenaS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscit/VudadhaPVS12,
author = {Chetan Vudadha and
Phaneendra P. Sai and
Sreehari Veeramachaneni and
M. B. Srinivas},
title = {{CNFET} based ternary magnitude comparator},
booktitle = {International Symposium on Communications and Information Technologies,
{ISCIT} 2012, Gold Coast, Australia, October 2-5, 2012},
pages = {942--946},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISCIT.2012.6381040},
doi = {10.1109/ISCIT.2012.6381040},
timestamp = {Mon, 08 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscit/VudadhaPVS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ised/AhmedAVMS12,
author = {Syed Ershad Ahmed and
Sibi Abraham and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
M. B. Srinivas},
title = {A Modified Twin Precision Multiplier with 2D Bypassing Technique},
booktitle = {International Symposium on Electronic System Design, ISEDs 2012, Kolkata,
India, December 19-22, 2012},
pages = {102--106},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISED.2012.58},
doi = {10.1109/ISED.2012.58},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ised/AhmedAVMS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/VudadhaPVAMS12,
author = {Chetan Vudadha and
P. Sai Phaneendra and
Sreehari Veeramachaneni and
Syed Ershad Ahmed and
N. Moorthy Muthukrishnan and
Mandalika B. Srinivas},
title = {Design of Prefix-Based Optimal Reversible Comparator},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2012, Amherst,
MA, USA, August 19-21, 2012},
pages = {201--206},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/ISVLSI.2012.49},
doi = {10.1109/ISVLSI.2012.49},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/VudadhaPVAMS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/VudadhaPAVMS12,
author = {Chetan Vudadha and
P. Sai Phaneendra and
Syed Ershad Ahmed and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
Mandalika B. Srinivas},
title = {Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple
Hybrid Adders},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2012, Amherst,
MA, USA, August 19-21, 2012},
pages = {225--230},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/ISVLSI.2012.50},
doi = {10.1109/ISVLSI.2012.50},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/VudadhaPAVMS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/VudadhaMNPAVMS12,
author = {Chetan Vudadha and
Goutham Makkena and
M. Venkata Swamy Nayudu and
P. Sai Phaneendra and
Syed Ershad Ahmed and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
M. B. Srinivas},
editor = {Vishwani D. Agrawal and
Srimat T. Chakradhar},
title = {Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive
Resolution Flash ADCs},
booktitle = {25th International Conference on {VLSI} Design, Hyderabad, India,
January 7-11, 2012},
pages = {280--285},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/VLSID.2012.84},
doi = {10.1109/VLSID.2012.84},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/VudadhaMNPAVMS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/VPAVMS11,
author = {Chetan Kumar V. and
P. Sai Phaneendra and
Syed Ershad Ahmed and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
M. B. Srinivas},
title = {A Unified Architecture for {BCD} and Binary Adder/Subtractor},
booktitle = {14th Euromicro Conference on Digital System Design, Architectures,
Methods and Tools, {DSD} 2011, August 31 - September 2, 2011, Oulu,
Finland},
pages = {426--429},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/DSD.2011.58},
doi = {10.1109/DSD.2011.58},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/VPAVMS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscit/PVAVMS11,
author = {P. Sai Phaneendra and
Chetan Vudadha and
Syed Ershad Ahmed and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
M. B. Srinivas},
title = {Increment/decrement/2's complement/priority encoder circuit for varying
operand lengths},
booktitle = {11th International Symposium on Communications and Information Technologies,
{ISCIT} 2011, Hangzhou, China, October 12-14, 2011},
pages = {472--477},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISCIT.2011.6092152},
doi = {10.1109/ISCIT.2011.6092152},
timestamp = {Mon, 08 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscit/PVAVMS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ised/AdimulamMVMS11,
author = {Mahesh Kumar Adimulam and
Krishna Kumar Movva and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
M. B. Srinivas},
title = {A Multiple-Bandwidth 10-bit {SAR} Analog to Digital Converter},
booktitle = {International Symposium on Electronic System Design, {ISED} 2011,
Kochi, Kerala, India, December 19-21, 2011},
pages = {24--29},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ISED.2011.63},
doi = {10.1109/ISED.2011.63},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ised/AdimulamMVMS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ised/VPAVMS11,
author = {Chetan Kumar V. and
P. Sai Phaneendra and
Syed Ershad Ahmed and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
M. B. Srinivas},
title = {A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with
Improved Decision Block},
booktitle = {International Symposium on Electronic System Design, {ISED} 2011,
Kochi, Kerala, India, December 19-21, 2011},
pages = {100--105},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ISED.2011.52},
doi = {10.1109/ISED.2011.52},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ised/VPAVMS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/VPAVMS11,
author = {Chetan Kumar V. and
Sai Phaneendra P. and
Syed Ershad Ahmed and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
M. B. Srinivas},
title = {A Prefix Based Reconfigurable Adder},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2011, 4-6
July 2011, Chennai, India},
pages = {349--350},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ISVLSI.2011.69},
doi = {10.1109/ISVLSI.2011.69},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/VPAVMS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/SainiKVS10,
author = {Sandeep Saini and
A. Mahesh Kumar and
Sreehari Veeramachaneni and
M. B. Srinivas},
title = {An Alternate Approach to Buffer Insertion for Delay and Power Reduction
in {VLSI} Interconnects},
journal = {J. Low Power Electron.},
volume = {6},
number = {3},
pages = {429--435},
year = {2010},
url = {https://doi.org/10.1166/jolpe.2010.1090},
doi = {10.1166/JOLPE.2010.1090},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jolpe/SainiKVS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/AdimulamMVMS10,
author = {Mahesh Kumar Adimulam and
Krishna Kumar Movva and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
Mandalika B. Srinivas},
title = {Low power, variable resolution pipelined analog to Digital converter
with sub flash architecture},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2010,
Kuala Lumpur, Malaysia, December 6-9, 2010},
pages = {204--207},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/APCCAS.2010.5774898},
doi = {10.1109/APCCAS.2010.5774898},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/apccas/AdimulamMVMS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/SainiMM10,
author = {Sandeep Saini and
Anurag Mahajan and
Srinivas B. Mandalika},
title = {Implementation of low power {FFT} structure using a method based on
conditionally coded blocks},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2010,
Kuala Lumpur, Malaysia, December 6-9, 2010},
pages = {935--938},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/APCCAS.2010.5774872},
doi = {10.1109/APCCAS.2010.5774872},
timestamp = {Fri, 02 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/apccas/SainiMM10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/KalyanS10,
author = {Gudipati Kalyan and
M. B. Srinivas},
title = {An efficient {ODT} calibration scheme for improved signal integrity
in memory interface},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2010,
Kuala Lumpur, Malaysia, December 6-9, 2010},
pages = {1211--1214},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/APCCAS.2010.5775020},
doi = {10.1109/APCCAS.2010.5775020},
timestamp = {Wed, 17 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/apccas/KalyanS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/AdimulamMVMS10,
author = {Mahesh Kumar Adimulam and
Krishna Kumar Movva and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
M. B. Srinivas},
editor = {R. Iris Bahar and
Fabrizio Lombardi and
David Atienza and
Erik Brunvand},
title = {A low power, variable resolution two-step flash {ADC}},
booktitle = {Proceedings of the 20th {ACM} Great Lakes Symposium on {VLSI} 2009,
Providence, Rhode Island, USA, May 16-18 2010},
pages = {39--44},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1785481.1785492},
doi = {10.1145/1785481.1785492},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/AdimulamMVMS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icwet/JamwalSSK10,
author = {Pradeep Jamwal and
M. B. Srinivas and
G. V. K. Sarma and
M. Murali Krishna},
editor = {B. K. Mishra},
title = {A new approach to minimize leakage power in nano-scale {VLSI} adder},
booktitle = {Proceedings of the {ICWET} '10 International Conference {\&} Workshop
on Emerging Trends in Technology, Mumbai, Maharashtra, India, February
26 - 27, 2010},
pages = {880--886},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1741906.1742108},
doi = {10.1145/1741906.1742108},
timestamp = {Tue, 26 Feb 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icwet/JamwalSSK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipccc/IyerIMPSS10,
author = {Vasanth Iyer and
S. Sitharama Iyengar and
Garimella Rama Murthy and
Nandan Parameswaran and
Dhananjay Singh and
Mandalika B. Srinivas},
title = {Effects of channel {SNR} in mobile cognitive radios and coexisting
deployment of cognitive wireless sensor networks},
booktitle = {29th International Performance Computing and Communications Conference,
{IPCCC} 2010, 9-11 December 2010, Albuquerque, NM, {USA}},
pages = {294--301},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/PCCC.2010.5682296},
doi = {10.1109/PCCC.2010.5682296},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipccc/IyerIMPSS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/AdimulamVMS10,
author = {Mahesh Kumar Adimulam and
Sreehari Veeramachaneni and
N. Moorthy Muthukrishnan and
M. B. Srinivas},
title = {A Novel, Variable Resolution Flash {ADC} with Sub Flash Architecture},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2010, 5-7
July 2010, Lixouri Kefalonia, Greece},
pages = {434--435},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/ISVLSI.2010.68},
doi = {10.1109/ISVLSI.2010.68},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/AdimulamVMS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/SainiAVS10,
author = {Sandeep Saini and
Mahesh Kumar Adimulam and
Sreehari Veeramachaneni and
M. B. Srinivas},
title = {An Alternative approach to Buffer Insertion for Delay and Power Reduction
in {VLSI} Interconnects},
booktitle = {{VLSI} Design 2010: 23rd International Conference on {VLSI} Design,
9th International Conference on Embedded Systems, Bangalore, India,
3-7 January 2010},
pages = {411--416},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/VLSI.Design.2010.53},
doi = {10.1109/VLSI.DESIGN.2010.53},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/SainiAVS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/AdimulamVS09,
author = {Mahesh Kumar Adimulam and
Sreehari Veeramachaneni and
M. B. Srinivas},
title = {A Novel Low Power, Variable Resolution Flash Analog-to-Digital Converter},
journal = {J. Low Power Electron.},
volume = {5},
number = {3},
pages = {279--290},
year = {2009},
url = {https://doi.org/10.1166/jolpe.2009.1029},
doi = {10.1166/JOLPE.2009.1029},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jolpe/AdimulamVS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcos/ThapliyalAS09,
author = {Himanshu Thapliyal and
Hamid R. Arabnia and
M. B. Srinivas},
title = {Efficient Reversible Logic Design of {BCD} Subtractors},
journal = {Trans. Comput. Sci.},
volume = {3},
pages = {99--121},
year = {2009},
url = {https://doi.org/10.1007/978-3-642-00212-0\_6},
doi = {10.1007/978-3-642-00212-0\_6},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcos/ThapliyalAS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/BharghavaS09,
author = {Abinesh Ramachandran and
Bharghava Rajaram and
Mandalika B. Srinivas},
title = {Transition Inversion Based Low Power Data Coding Scheme for Synchronous
Serial Communication},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2009, 13-15
May 2009, Tampa, Florida, {USA}},
pages = {103--108},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ISVLSI.2009.43},
doi = {10.1109/ISVLSI.2009.43},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/BharghavaS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/SinghGVS09,
author = {Anshul Singh and
Aman Gupta and
Sreehari Veeramachaneni and
M. B. Srinivas},
title = {A High Performance Unified {BCD} and Binary Adder/Subtractor},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2009, 13-15
May 2009, Tampa, Florida, {USA}},
pages = {211--216},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ISVLSI.2009.40},
doi = {10.1109/ISVLSI.2009.40},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/SinghGVS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/RamasahayamS09,
author = {Swathi Ramasahayam and
M. B. Srinivas},
title = {All Digital Duty Cycle Correction Circuit in 90nm Based on Mutex},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2009, 13-15
May 2009, Tampa, Florida, {USA}},
pages = {258--262},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ISVLSI.2009.41},
doi = {10.1109/ISVLSI.2009.41},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/RamasahayamS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iwcmc/IyerIMHPS09,
author = {Vasanth Iyer and
S. Sitharama Iyengar and
Garimella Rama Murthy and
Bertrand Hochet and
Vir V. Phoha and
M. B. Srinivas},
editor = {Mohsen Guizani and
Peter M{\"{u}}ller and
Klaus{-}Peter F{\"{a}}hnrich and
Athanasios V. Vasilakos and
Yan Zhang and
Jun Zhang},
title = {Multi-hop scheduling and local data link aggregation dependant Qos
in modeling and simulation of power-aware wireless sensor networks},
booktitle = {Proceedings of the International Conference on Wireless Communications
and Mobile Computing: Connecting the World Wirelessly, {IWCMC} 2009,
Leipzig, Germany, June 21-24, 2009},
pages = {844--848},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1582379.1582562},
doi = {10.1145/1582379.1582562},
timestamp = {Tue, 20 Aug 2024 07:54:44 +0200},
biburl = {https://dblp.org/rec/conf/iwcmc/IyerIMHPS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/AdimulamVS09,
author = {Mahesh Kumar Adimulam and
Sreehari Veeramachaneni and
M. B. Srinivas},
title = {A novel low power, variable resolution pipelined {ADC}},
booktitle = {Annual {IEEE} International SoC Conference, SoCC 2009, September 9-11,
2009, Belfast, Northern Ireland, UK, Proceedings},
pages = {183--186},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/SOCCON.2009.5398061},
doi = {10.1109/SOCCON.2009.5398061},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/socc/AdimulamVS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/VeeramachaneniKTS09,
author = {Sreehari Veeramachaneni and
Mahesh Kumar Adimulam and
Venkat Tummala and
M. B. Srinivas},
title = {Design of a Low Power, Variable-Resolution Flash {ADC}},
booktitle = {{VLSI} Design 2009: Improving Productivity through Higher Abstraction,
The 22nd International Conference on {VLSI} Design, New Delhi, India,
5-9 January 2009},
pages = {117--122},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/VLSI.Design.2009.62},
doi = {10.1109/VLSI.DESIGN.2009.62},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/VeeramachaneniKTS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/RavindraS08,
author = {J. V. R. Ravindra and
M. B. Srinivas},
editor = {Vijaykrishnan Narayanan and
Zhiyuan Yan and
Enrico Macii and
Sanjukta Bhanja},
title = {Generic sub-space algorithm for generating reduced order models of
linear time varying vlsi circuits},
booktitle = {Proceedings of the 18th {ACM} Great Lakes Symposium on {VLSI} 2008,
Orlando, Florida, USA, May 4-6, 2008},
pages = {111--114},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1366110.1366138},
doi = {10.1145/1366110.1366138},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/RavindraS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/RaghunandanSS08,
author = {Chittarsu Raghunandan and
K. S. Sainarayanan and
M. B. Srinivas},
title = {Process Variation Aware Bus-Coding Scheme for Delay Minimization in
{VLSI} Interconnects},
booktitle = {9th International Symposium on Quality of Electronic Design {(ISQED}
2008), 17-19 March 2008, San Jose, CA, {USA}},
pages = {43--46},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ISQED.2008.4479695},
doi = {10.1109/ISQED.2008.4479695},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/RaghunandanSS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/AvinashMS08,
author = {Lingamneni Avinash and
Kirthi Krishna Muntimadugu and
M. B. Srinivas},
title = {A Novel Encoding Scheme for Delay and Energy Minimization in {VLSI}
Interconnects with Built-In Error Detection},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2008, 7-9
April 2008, Montpellier, France},
pages = {128--133},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ISVLSI.2008.51},
doi = {10.1109/ISVLSI.2008.51},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/AvinashMS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sutc/IyerGS08,
author = {Vasanth Iyer and
Rammurthy Garimella and
M. B. Srinivas},
editor = {Mukesh Singhal and
Giovanna Di Marzo Serugendo and
Jeffrey J. P. Tsai and
Wang{-}Chien Lee and
Kay R{\"{o}}mer and
Yu{-}Chee Tseng and
Han C. W. Hsiao},
title = {Training Data Compression Algorithms and Reliability in Large Wireless
Sensor Networks},
booktitle = {{IEEE} International Conference on Sensor Networks, Ubiquitous, and
Trustworthy Computing {(SUTC} 2008), 11-13 June 2008, Taichung, Taiwan},
pages = {480--485},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/SUTC.2008.48},
doi = {10.1109/SUTC.2008.48},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sutc/IyerGS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/VeeramachaneniKVSSS08,
author = {Sreehari Veeramachaneni and
Kirthi M. Krishna and
Prateek G. V. and
Subroto S. and
Bharat S. and
M. B. Srinivas},
title = {A Novel Carry-Look Ahead Approach to a Unified {BCD} and Binary Adder/Subtractor},
booktitle = {21st International Conference on {VLSI} Design {(VLSI} Design 2008),
4-8 January 2008, Hyderabad, India},
pages = {547--552},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/VLSI.2008.80},
doi = {10.1109/VLSI.2008.80},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/VeeramachaneniKVSSS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/RavindraS07,
author = {J. V. R. Ravindra and
M. B. Srinivas},
title = {Delay and Energy Efficient Coding Techniques for Capacitive Interconnects},
journal = {J. Circuits Syst. Comput.},
volume = {16},
number = {6},
pages = {929--942},
year = {2007},
url = {https://doi.org/10.1142/S0218126607004106},
doi = {10.1142/S0218126607004106},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/RavindraS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/monet/SudhakarKS07,
author = {M. Sudhakar and
Ramachandruni Venkata Kamala and
M. B. Srinivas},
title = {New and Improved Architectures for Montgomery Modular Multiplication},
journal = {Mob. Networks Appl.},
volume = {12},
number = {4},
pages = {281--291},
year = {2007},
url = {https://doi.org/10.1007/s11036-007-0019-z},
doi = {10.1007/S11036-007-0019-Z},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/monet/SudhakarKS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/RavindraS07,
author = {J. V. R. Ravindra and
M. B. Srinivas},
title = {A Statistical Model for Estimating the Effect of Process Variations
on Delay and Slew Metrics for {VLSI} Interconnects},
booktitle = {Tenth Euromicro Conference on Digital System Design: Architectures,
Methods and Tools {(DSD} 2007), 29-31 August 2007, L{\"{u}}beck,
Germany},
pages = {325--330},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/DSD.2007.4341488},
doi = {10.1109/DSD.2007.4341488},
timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
biburl = {https://dblp.org/rec/conf/dsd/RavindraS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/foci/KalaS07,
author = {Keerthi Laal Kala and
M. B. Srinivas},
title = {Rule Selection in Fuzzy Systems using Heuristics and Branch Prediction},
booktitle = {Proceedings of the {IEEE} Symposium on Foundations of Computational
Intelligence, {FOCI} 2007, part of the {IEEE} Symposium Series on
Computational Intelligence 2007, Honolulu, Hawaii, USA, 1-5 April
2007},
pages = {603--607},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/FOCI.2007.371534},
doi = {10.1109/FOCI.2007.371534},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/foci/KalaS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/globecom/MittalKS07,
author = {Shashank Mittal and
Md. Zafar Ali Khan and
M. B. Srinivas},
title = {Area Efficient High Speed Architecture of Bruun's {FFT} for Software
Defined Radio},
booktitle = {Proceedings of the Global Communications Conference, 2007. {GLOBECOM}
'07, Washington, DC, USA, 26-30 November 2007},
pages = {3118--3122},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/GLOCOM.2007.590},
doi = {10.1109/GLOCOM.2007.590},
timestamp = {Tue, 23 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/globecom/MittalKS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/VeeramachaneniAKS07,
author = {Sreehari Veeramachaneni and
Lingamneni Avinash and
Kirthi M. Krishna and
M. B. Srinivas},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Novel architectures for efficient (m, n) parallel counters},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {188--191},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228833},
doi = {10.1145/1228784.1228833},
timestamp = {Wed, 16 Aug 2023 21:16:32 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/VeeramachaneniAKS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/RaghunandanSS07,
author = {Chittarsu Raghunandan and
K. S. Sainarayanan and
M. B. Srinivas},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Bus-encoding technique to reduce delay, power and simultaneous switching
noise {(SSN)} in {RLC} interconnects},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {371--376},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228873},
doi = {10.1145/1228784.1228873},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/RaghunandanSS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/RaghunandanSS07,
author = {Chittarsu Raghunandan and
K. S. Sainarayanan and
M. B. Srinivas},
title = {Area Efficient Bus Encoding Technique for Minimizing Simultaneous
Switching Noise {(SSN)}},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2007), 27-20
May 2007, New Orleans, Louisiana, {USA}},
pages = {1129--1132},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISCAS.2007.378209},
doi = {10.1109/ISCAS.2007.378209},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/RaghunandanSS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/VeeramachaneniKASS07,
author = {Sreehari Veeramachaneni and
Kirthi M. Krishna and
Lingamneni Avinash and
Reddy Puppala Sreekanth and
M. B. Srinivas},
title = {Novel High-Speed Redundant Binary to Binary converter using Prefix
Networks},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2007), 27-20
May 2007, New Orleans, Louisiana, {USA}},
pages = {3271--3274},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISCAS.2007.378170},
doi = {10.1109/ISCAS.2007.378170},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/VeeramachaneniKASS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/VeeramachaneniKASS07,
author = {Sreehari Veeramachaneni and
Kirthi M. Krishna and
Lingamneni Avinash and
Reddy Puppala Sreekanth and
M. B. Srinivas},
title = {Novel, High-Speed 16-Digit {BCD} Adders Conforming to {IEEE} 754r
Format},
booktitle = {2007 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2007), May 9-11, 2007, Porto Alegre, Brazil},
pages = {343--350},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ISVLSI.2007.71},
doi = {10.1109/ISVLSI.2007.71},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/VeeramachaneniKASS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/SainarayananRS07,
author = {K. S. Sainarayanan and
Chittarsu Raghunandan and
M. B. Srinivas},
title = {Delay and Power Minimization in {VLSI} Interconnects with Spatio-Temporal
Bus-Encoding Scheme},
booktitle = {2007 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2007), May 9-11, 2007, Porto Alegre, Brazil},
pages = {401--408},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ISVLSI.2007.35},
doi = {10.1109/ISVLSI.2007.35},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/SainarayananRS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nanonet/RavindraS07,
author = {J. V. R. Ravindra and
M. B. Srinivas},
editor = {Salvatore Coffa},
title = {Generating reduced order models using subspace iteration for linear
{RLC} circuits in nanometer designs},
booktitle = {2nd Internationa {ICST} Conference on Nano-Networks, Nano-Net 2007,
Catania, Italy, September 24-26, 2007},
pages = {25},
publisher = {{ICST/ACM}},
year = {2007},
url = {https://doi.org/10.4108/ICST.NANONET2007.2084},
doi = {10.4108/ICST.NANONET2007.2084},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/nanonet/RavindraS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/samos/MittalKS07,
author = {Shashank Mittal and
Md. Zafar Ali Khan and
M. B. Srinivas},
editor = {Stamatis Vassiliadis and
Mladen Berekovic and
Timo D. H{\"{a}}m{\"{a}}l{\"{a}}inen},
title = {A Comparative Study of Different {FFT} Architectures for Software
Defined Radio},
booktitle = {Embedded Computer Systems: Architectures, Modeling, and Simulation,
7th International Workshop, {SAMOS} 2007, Samos, Greece, July 16-19,
2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4599},
pages = {375--384},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-73625-7\_39},
doi = {10.1007/978-3-540-73625-7\_39},
timestamp = {Tue, 14 May 2019 10:00:45 +0200},
biburl = {https://dblp.org/rec/conf/samos/MittalKS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/MaddiS07,
author = {Sudhakar Maddi and
M. B. Srinivas},
editor = {Antonio Petraglia and
Volnei A. Pedroni and
Gert Cauwenberghs},
title = {A unified and reconfigurable Montgomery Multiplier architecture without
four-to-two {CSA}},
booktitle = {Proceedings of the 20th Annual Symposium on Integrated Circuits and
Systems Design, {SBCCI} 2007, Copacabana, Rio de Janeiro, Brazil,
September 3-6, 2007},
pages = {147--152},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1284480.1284525},
doi = {10.1145/1284480.1284525},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sbcci/MaddiS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/SainarayananRS07,
author = {K. S. Sainarayanan and
Chittarsu Raghunandan and
M. B. Srinivas},
editor = {Antonio Petraglia and
Volnei A. Pedroni and
Gert Cauwenberghs},
title = {Bus encoding schemes for minimizing delay in {VLSI} interconnects},
booktitle = {Proceedings of the 20th Annual Symposium on Integrated Circuits and
Systems Design, {SBCCI} 2007, Copacabana, Rio de Janeiro, Brazil,
September 3-6, 2007},
pages = {184--189},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1284480.1284533},
doi = {10.1145/1284480.1284533},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sbcci/SainarayananRS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/JayanthiM07,
author = {J. V. R. Ravindra and
Srinivas Bala Mandalika},
editor = {Antonio Petraglia and
Volnei A. Pedroni and
Gert Cauwenberghs},
title = {Modeling and analysis of crosstalk for distributed {RLC} interconnects
using difference model approach},
booktitle = {Proceedings of the 20th Annual Symposium on Integrated Circuits and
Systems Design, {SBCCI} 2007, Copacabana, Rio de Janeiro, Brazil,
September 3-6, 2007},
pages = {207--211},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1284480.1284538},
doi = {10.1145/1284480.1284538},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sbcci/JayanthiM07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SudhakarKS07,
author = {M. Sudhakar and
Ramachandruni Venkata Kamala and
M. B. Srinivas},
title = {A bit-sliced, scalable and unified montgomery multiplier architecture
for {RSA} and {ECC}},
booktitle = {{IFIP} VLSI-SoC 2007, {IFIP} {WG} 10.5 International Conference on
Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA,
15-17 October 2007},
pages = {252--257},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/VLSISOC.2007.4402507},
doi = {10.1109/VLSISOC.2007.4402507},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SudhakarKS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/VeeramachaneniKAPS07,
author = {Sreehari Veeramachaneni and
Kirthi M. Krishna and
Lingamneni Avinash and
Reddy Puppala Sreekanth and
M. B. Srinivas},
title = {Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2
Compressors},
booktitle = {20th International Conference on {VLSI} Design {(VLSI} Design 2007),
Sixth International Conference on Embedded Systems {(ICES} 2007),
6-10 January 2007, Bangalore, India},
pages = {324--329},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/VLSID.2007.116},
doi = {10.1109/VLSID.2007.116},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/VeeramachaneniKAPS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/SudhakarKS07,
author = {M. Sudhakar and
Ramachandruni Venkata Kamala and
M. B. Srinivas},
title = {A Unified, Reconfigurable Architecture for Montgomery Multiplication
in Finite Fields GF(p) and GF(2{\^{}}n)},
booktitle = {20th International Conference on {VLSI} Design {(VLSI} Design 2007),
Sixth International Conference on Embedded Systems {(ICES} 2007),
6-10 January 2007, Bangalore, India},
pages = {750--755},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/VLSID.2007.27},
doi = {10.1109/VLSID.2007.27},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/SudhakarKS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aPcsac/ThapliyalS06,
author = {Himanshu Thapliyal and
M. B. Srinivas},
editor = {Chris R. Jesshope and
Colin Egan},
title = {The New {BCD} Subtractor and Its Reversible Logic Implementation},
booktitle = {Advances in Computer Systems Architecture, 11th Asia-Pacific Conference,
{ACSAC} 2006, Shanghai, China, September 6-8, 2006, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4186},
pages = {466--472},
publisher = {Springer},
year = {2006},
url = {https://doi.org/10.1007/11859802\_45},
doi = {10.1007/11859802\_45},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aPcsac/ThapliyalS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aiccsa/ThapliyalGKS06,
author = {Himanshu Thapliyal and
Neela Gopi and
K. K. Pavan Kumar and
M. B. Srinivas},
title = {Low Power Hierarchical Multiplier and Carry Look-Ahead Architecture},
booktitle = {2006 {IEEE/ACS} International Conference on Computer Systems and Applications
{(AICCSA} 2006), March 8-11, Dubai/Sharjah, {UAE}},
pages = {88--92},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/AICCSA.2006.205072},
doi = {10.1109/AICCSA.2006.205072},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aiccsa/ThapliyalGKS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aiccsa/ThapliyalS06,
author = {Himanshu Thapliyal and
M. B. Srinivas},
title = {Novel Reversible Multiplier Architecture Using Reversible {TSG} Gate},
booktitle = {2006 {IEEE/ACS} International Conference on Computer Systems and Applications
{(AICCSA} 2006), March 8-11, Dubai/Sharjah, {UAE}},
pages = {100--103},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/AICCSA.2006.205074},
doi = {10.1109/AICCSA.2006.205074},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aiccsa/ThapliyalS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/KalaS06,
author = {Keerthi Laal Kala and
M. B. Srinivas},
title = {A Generic Architecture for Intelligent System Hardware},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems 2006, {APCCAS}
2006, Singapore, 4-7 December 2006},
pages = {321--326},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/APCCAS.2006.342416},
doi = {10.1109/APCCAS.2006.342416},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/apccas/KalaS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/csreaESA/GopineediTSA06,
author = {Pallavi Devi Gopineedi and
Himanshu Thapliyal and
M. B. Srinivas and
Hamid R. Arabnia},
editor = {Hamid R. Arabnia},
title = {Novel and Efficient 4: 2 and 5: 2 Compressors with Minimum Number
of Transistors Designed for Low-Power Operations},
booktitle = {Proceedings of the 2006 International Conference on Embedded Systems
{\&} Applications, Las Vegas, Nevada, USA, June 26-29, 2006},
pages = {160--168},
publisher = {{CSREA} Press},
year = {2006},
timestamp = {Tue, 02 Jan 2007 10:07:25 +0100},
biburl = {https://dblp.org/rec/conf/csreaESA/GopineediTSA06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/delta/SainarayananRS06,
author = {K. S. Sainarayanan and
J. V. R. Ravindra and
M. B. Srinivas},
title = {Minimizing Simultaneous Switching Noise {(SSN)} using Modified Odd/Even
Bus Invert Method},
booktitle = {Third {IEEE} International Workshop on Electronic Design, Test and
Applications {(DELTA} 2006), 17-19 January 2006, Kuala Lumpur, Malaysia},
pages = {336--339},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/DELTA.2006.68},
doi = {10.1109/DELTA.2006.68},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/delta/SainarayananRS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/delta/ThapliyalRKGS06,
author = {Himanshu Thapliyal and
Anvesh Ramasahayam and
Vivek Reddy Kotha and
Kunul Gottimukkula and
M. B. Srinivas},
title = {Modified Montgomery Modular Multiplication Using 4: 2 Compressor and
{CSA} Adder},
booktitle = {Third {IEEE} International Workshop on Electronic Design, Test and
Applications {(DELTA} 2006), 17-19 January 2006, Kuala Lumpur, Malaysia},
pages = {414--417},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/DELTA.2006.70},
doi = {10.1109/DELTA.2006.70},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/delta/ThapliyalRKGS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/KamalaSS06,
author = {Ramachandruni Venkata Kamala and
M. Sudhakar and
M. B. Srinivas},
title = {An Efficient Reconfigurable Montgomery Multiplier Architecture for
GF(n)},
booktitle = {Ninth Euromicro Conference on Digital System Design: Architectures,
Methods and Tools {(DSD} 2006), 30 August - 1 September 2006, Dubrovnik,
Croatia},
pages = {155--159},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/DSD.2006.23},
doi = {10.1109/DSD.2006.23},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/KamalaSS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SainarayananRS06,
author = {K. S. Sainarayanan and
J. V. R. Ravindra and
M. B. Srinivas},
title = {A novel, coupling driven, low power bus coding technique for minimizing
capacitive crosstalk in {VLSI} interconnects},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1693544},
doi = {10.1109/ISCAS.2006.1693544},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/SainarayananRS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KamalaS06,
author = {Ramachandruni Venkata Kamala and
M. B. Srinivas},
title = {High-Throughput Montgomery Modular Multiplication},
booktitle = {{IFIP} VLSI-SoC 2006, {IFIP} {WG} 10.5 International Conference on
Very Large Scale Integration of System-on-Chip, Nice, France, 16-18
October 2006},
pages = {58--62},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/VLSISOC.2006.313204},
doi = {10.1109/VLSISOC.2006.313204},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KamalaS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/ThapliyalKS06,
author = {Himanshu Thapliyal and
Saurabh Kotiyal and
M. B. Srinivas},
title = {Novel {BCD} Adders and Their Reversible Logic Implementation for {IEEE}
754r Format},
booktitle = {19th International Conference on {VLSI} Design {(VLSI} Design 2006),
3-7 January 2006, Hyderabad, India},
pages = {387--392},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/VLSID.2006.122},
doi = {10.1109/VLSID.2006.122},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/ThapliyalKS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-cs-0603088,
author = {Himanshu Thapliyal and
Saurabh Kotiyal and
M. B. Srinivas},
title = {Novel {BCD} Adders and Their Reversible Logic Implementation for {IEEE}
754r Format},
journal = {CoRR},
volume = {abs/cs/0603088},
year = {2006},
url = {http://arxiv.org/abs/cs/0603088},
eprinttype = {arXiv},
eprint = {cs/0603088},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-cs-0603088.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-cs-0603091,
author = {Himanshu Thapliyal and
M. B. Srinivas},
title = {A New Reversible {TSG} Gate and Its Application For Designing Efficient
Adder Circuits},
journal = {CoRR},
volume = {abs/cs/0603091},
year = {2006},
url = {http://arxiv.org/abs/cs/0603091},
eprinttype = {arXiv},
eprint = {cs/0603091},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-cs-0603091.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-cs-0603092,
author = {Himanshu Thapliyal and
M. B. Srinivas},
title = {An Extension to {DNA} Based Fredkin Gate Circuits: Design of Reversible
Sequential Circuits using Fredkin Gates},
journal = {CoRR},
volume = {abs/cs/0603092},
year = {2006},
url = {http://arxiv.org/abs/cs/0603092},
eprinttype = {arXiv},
eprint = {cs/0603092},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-cs-0603092.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-cs-0605004,
author = {Himanshu Thapliyal and
M. B. Srinivas},
title = {Novel Reversible Multiplier Architecture Using Reversible {TSG} Gate},
journal = {CoRR},
volume = {abs/cs/0605004},
year = {2006},
url = {http://arxiv.org/abs/cs/0605004},
eprinttype = {arXiv},
eprint = {cs/0605004},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-cs-0605004.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-cs-0609023,
author = {Himanshu Thapliyal and
M. B. Srinivas},
title = {Novel Reversible {TSG} Gate and Its Application for Designing Components
of Primitive Reversible/Quantum {ALU}},
journal = {CoRR},
volume = {abs/cs/0609023},
year = {2006},
url = {http://arxiv.org/abs/cs/0609023},
eprinttype = {arXiv},
eprint = {cs/0609023},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-cs-0609023.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-cs-0609028,
author = {Himanshu Thapliyal and
M. B. Srinivas},
title = {{VLSI} Implementation of {RSA} Encryption System Using Ancient Indian
Vedic Mathematics},
journal = {CoRR},
volume = {abs/cs/0609028},
year = {2006},
url = {http://arxiv.org/abs/cs/0609028},
eprinttype = {arXiv},
eprint = {cs/0609028},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-cs-0609028.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-cs-0609036,
author = {Himanshu Thapliyal and
Hamid R. Arabnia and
M. B. Srinivas},
title = {Reduced Area Low Power High Throughput {BCD} Adders for {IEEE} 754r
Format},
journal = {CoRR},
volume = {abs/cs/0609036},
year = {2006},
url = {http://arxiv.org/abs/cs/0609036},
eprinttype = {arXiv},
eprint = {cs/0609036},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-cs-0609036.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aPcsac/ThapliyalS05,
author = {Himanshu Thapliyal and
M. B. Srinivas},
editor = {Thambipillai Srikanthan and
Jingling Xue and
Chip{-}Hong Chang},
title = {A Novel Reversible {TSG} Gate and Its Application for Designing Reversible
Carry Look-Ahead and Other Adder Architectures},
booktitle = {Advances in Computer Systems Architecture, 10th Asia-Pacific Conference,
{ACSAC} 2005, Singapore, October 24-26, 2005, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3740},
pages = {805--817},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11572961\_66},
doi = {10.1007/11572961\_66},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aPcsac/ThapliyalS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/amcs/ThapliyalSA05,
author = {Himanshu Thapliyal and
M. B. Srinivas and
Hamid R. Arabnia},
editor = {Hamid R. Arabnia and
Iyad A. Ajwa},
title = {Design And Analysis of {A} {VLSI} Based High Performance Low Power
Parallel Square Architecture},
booktitle = {Proceedings of the 2005 International Conference on Algorithmic Mathematics
and Computer Science, {AMCS} 2005, Las Vegas, Nevada, {USA}},
pages = {72--76},
publisher = {{CSREA} Press},
year = {2005},
timestamp = {Fri, 27 Jan 2006 09:13:50 +0100},
biburl = {https://dblp.org/rec/conf/amcs/ThapliyalSA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cdes/ThapliyalSRA05,
author = {Himanshu Thapliyal and
M. B. Srinivas and
Rameshwar Rao and
Hamid R. Arabnia},
editor = {Laurence Tianruo Yang and
Hamid R. Arabnia and
Yiming Li and
Salam N. Salloum and
Jos{\'{e}} G. Delgado{-}Frias},
title = {Verilog Coding Style for Efficient Synthesis In {FPGA}},
booktitle = {Proceedings of the 2005 International Conference on Computer Design,
{CDES} 2005, Las Vegas, Nevada, USA, June 27-30, 2005},
pages = {85--90},
publisher = {{CSREA} Press},
year = {2005},
timestamp = {Mon, 10 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cdes/ThapliyalSRA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cdes/ThapliyalSA05,
author = {Himanshu Thapliyal and
M. B. Srinivas and
Hamid R. Arabnia},
editor = {Laurence Tianruo Yang and
Hamid R. Arabnia and
Yiming Li and
Salam N. Salloum and
Jos{\'{e}} G. Delgado{-}Frias},
title = {Design for {A} Fast And Low Power 2's Complement Multiplier},
booktitle = {Proceedings of the 2005 International Conference on Computer Design,
{CDES} 2005, Las Vegas, Nevada, USA, June 27-30, 2005},
pages = {165--167},
publisher = {{CSREA} Press},
year = {2005},
timestamp = {Thu, 02 Feb 2006 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cdes/ThapliyalSA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/csc/KotiyalTSA05,
author = {Saurabh Kotiyal and
Himanshu Thapliyal and
M. B. Srinivas and
Hamid R. Arabnia},
editor = {Hamid R. Arabnia and
George A. Gravvanis},
title = {{VLSI} Implementation of O(n*n) Sorting Algorithms And Their Hardware
Comparison},
booktitle = {Proceedings of The 2005 International Conference on Scientific Computing,
{CSC} 2005, Las Vegas, Nevada, USA, June 20-23, 2005},
pages = {74--77},
publisher = {{CSREA} Press},
year = {2005},
timestamp = {Tue, 02 Jan 2007 09:04:05 +0100},
biburl = {https://dblp.org/rec/conf/csc/KotiyalTSA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/csreaESA/ThapliyalSA05,
author = {Himanshu Thapliyal and
M. B. Srinivas and
Hamid R. Arabnia},
editor = {Laurence Tianruo Yang and
Hamid R. Arabnia and
J{\"{u}}rgen Becker and
Masaharu Imai and
Zoran A. Salcic},
title = {A Need of Quantum Computing: Reversible Logic Synthesis of Parallel
Binary Adder-Subtractor},
booktitle = {Proceedings of The 2005 International Conference on Embedded Systems
and Applications, {ESA} 2005, Las Vegas, Nevada, USA, June 27-30,
2005},
pages = {60--68},
publisher = {{CSREA} Press},
year = {2005},
timestamp = {Fri, 19 Jul 2019 13:02:47 +0200},
biburl = {https://dblp.org/rec/conf/csreaESA/ThapliyalSA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/csreaESA/ThapliyalSA05a,
author = {Himanshu Thapliyal and
M. B. Srinivas and
Hamid R. Arabnia},
editor = {Laurence Tianruo Yang and
Hamid R. Arabnia and
J{\"{u}}rgen Becker and
Masaharu Imai and
Zoran A. Salcic},
title = {A Reversible Version of 4 x 4 Bit Array Multiplier With Minimum Gates
and Garbage Outputs},
booktitle = {Proceedings of The 2005 International Conference on Embedded Systems
and Applications, {ESA} 2005, Las Vegas, Nevada, USA, June 27-30,
2005},
pages = {106--116},
publisher = {{CSREA} Press},
year = {2005},
timestamp = {Tue, 24 Jan 2006 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/csreaESA/ThapliyalSA05a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/csreaESA/ThapliyalSA05b,
author = {Himanshu Thapliyal and
M. B. Srinivas and
Hamid R. Arabnia},
editor = {Laurence Tianruo Yang and
Hamid R. Arabnia and
J{\"{u}}rgen Becker and
Masaharu Imai and
Zoran A. Salcic},
title = {Reversible Logic Synthesis of Half, Full and Parallel Subtractors},
booktitle = {Proceedings of The 2005 International Conference on Embedded Systems
and Applications, {ESA} 2005, Las Vegas, Nevada, USA, June 27-30,
2005},
pages = {165--181},
publisher = {{CSREA} Press},
year = {2005},
timestamp = {Tue, 24 Jan 2006 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/csreaESA/ThapliyalSA05b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/csreaSAM/ThapliyalSA05,
author = {Himanshu Thapliyal and
M. B. Srinivas and
Hamid R. Arabnia},
editor = {Hamid R. Arabnia},
title = {Faster {RSA} Encryption/Decryption Architecture Using an Efficient
High Speed Overlay Multiplier},
booktitle = {Proceedings of The 2005 International Conference on Security and Management,
{SAM} 2005, Las Vegas, Nevada, USA, June 20-23, 2005},
pages = {40--44},
publisher = {{CSREA} Press},
year = {2005},
timestamp = {Wed, 06 Dec 2006 10:55:26 +0100},
biburl = {https://dblp.org/rec/conf/csreaSAM/ThapliyalSA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/csreaSAM/ThapliyalSA05a,
author = {Himanshu Thapliyal and
M. B. Srinivas and
Hamid R. Arabnia},
editor = {Hamid R. Arabnia},
title = {Implementation of {A} Fast Square In {RSA} Encryption/Decryption Architecture},
booktitle = {Proceedings of The 2005 International Conference on Security and Management,
{SAM} 2005, Las Vegas, Nevada, USA, June 20-23, 2005},
pages = {371--374},
publisher = {{CSREA} Press},
year = {2005},
timestamp = {Wed, 06 Dec 2006 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/csreaSAM/ThapliyalSA05a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iastedCCS/SainarayananRS05,
author = {K. S. Sainarayanan and
J. V. R. Ravindra and
M. B. Srinivas},
editor = {Vojin G. Oklobdzija},
title = {A novel deep submicron low power bus coding technique},
booktitle = {Proceedings of the Third {IASTED} International Conference on Circuits,
Signals, and Systems, Marina del Rey, CA, USA, October 24-26, 2005},
pages = {154--159},
publisher = {{IASTED/ACTA} Press},
year = {2005},
timestamp = {Thu, 25 Jan 2007 13:41:15 +0100},
biburl = {https://dblp.org/rec/conf/iastedCCS/SainarayananRS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icnc/KalaS05,
author = {Keerthi Laal Kala and
M. B. Srinivas},
editor = {Lipo Wang and
Ke Chen and
Yew{-}Soon Ong},
title = {A 32-Bit Binary Floating Point Neuro-Chip},
booktitle = {Advances in Natural Computation, First International Conference, {ICNC}
2005, Changsha, China, August 27-29, 2005, Proceedings, Part {III}},
series = {Lecture Notes in Computer Science},
volume = {3612},
pages = {1015--1021},
publisher = {Springer},
year = {2005},
url = {https://doi.org/10.1007/11539902\_130},
doi = {10.1007/11539902\_130},
timestamp = {Sun, 02 Jun 2019 21:14:27 +0200},
biburl = {https://dblp.org/rec/conf/icnc/KalaS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itcc/NarvaneniS05,
author = {Yaswanth Narvaneni and
M. B. Srinivas},
title = {Local Language Support for Handheld Devices},
booktitle = {International Symposium on Information Technology: Coding and Computing
{(ITCC} 2005), Volume 2, 4-6 April 2005, Las Vegas, Nevada, {USA}},
pages = {799--800},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ITCC.2005.185},
doi = {10.1109/ITCC.2005.185},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itcc/NarvaneniS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ChakravarthyS03,
author = {K. Kalyan Chakravarthy and
M. B. Srinivas},
editor = {Hiroto Yasuura},
title = {Speech encoding and encryption in {VLSI}},
booktitle = {Proceedings of the 2003 Asia and South Pacific Design Automation Conference,
{ASP-DAC} '03, Kitakyushu, Japan, January 21-24, 2003},
pages = {569--570},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/1119772.1119895},
doi = {10.1145/1119772.1119895},
timestamp = {Thu, 11 Mar 2021 17:04:51 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/ChakravarthyS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KumarS03,
author = {I. Vijay Kumar and
M. B. Srinivas},
editor = {Hiroto Yasuura},
title = {Design of a digital {CDMA} receiver},
booktitle = {Proceedings of the 2003 Asia and South Pacific Design Automation Conference,
{ASP-DAC} '03, Kitakyushu, Japan, January 21-24, 2003},
pages = {587--588},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/1119772.1119904},
doi = {10.1145/1119772.1119904},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/KumarS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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