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ORCIDBibTeX records: Adit D. Singh
@inproceedings{DBLP:conf/ets/Singh24,
author = {Adit D. Singh},
title = {Silent Data Corruption from Timing Marginalities Due to Process Variations},
booktitle = {{IEEE} European Test Symposium, {ETS} 2024, The Hague, Netherlands,
May 20-24, 2024},
pages = {1--7},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/ETS61313.2024.10567054},
doi = {10.1109/ETS61313.2024.10567054},
timestamp = {Thu, 04 Jul 2024 15:45:26 +0200},
biburl = {https://dblp.org/rec/conf/ets/Singh24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/SinhaS24,
author = {Arani Sinha and
Adit D. Singh},
title = {Innovative Practices Track: Session 2 Silent Data Corruption},
booktitle = {42nd {IEEE} {VLSI} Test Symposium, {VTS} 2024, Tempe, AZ, USA, April
22-24, 2024},
pages = {1},
publisher = {{IEEE}},
year = {2024},
url = {https://doi.org/10.1109/VTS60656.2024.10538751},
doi = {10.1109/VTS60656.2024.10538751},
timestamp = {Mon, 03 Jun 2024 16:53:11 +0200},
biburl = {https://dblp.org/rec/conf/vts/SinhaS24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/latw/Singh23,
author = {Adit D. Singh},
title = {Silent Error Corruption: The New Reliability and Test Challenge},
booktitle = {24th {IEEE} Latin American Test Symposium, {LATS} 2023, Veracruz,
Mexico, March 21-24, 2023},
pages = {1--2},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/LATS58125.2023.10154487},
doi = {10.1109/LATS58125.2023.10154487},
timestamp = {Wed, 28 Jun 2023 16:25:05 +0200},
biburl = {https://dblp.org/rec/conf/latw/Singh23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/SinghCPG23,
author = {Adit D. Singh and
Sreejit Chakravarty and
George Papadimitriou and
Dimitris Gizopoulos},
title = {Silent Data Errors: Sources, Detection, and Modeling},
booktitle = {41st {IEEE} {VLSI} Test Symposium, {VTS} 2023, San Diego, CA, USA,
April 24-26, 2023},
pages = {1--12},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/VTS56346.2023.10139970},
doi = {10.1109/VTS56346.2023.10139970},
timestamp = {Fri, 09 Jun 2023 15:18:15 +0200},
biburl = {https://dblp.org/rec/conf/vts/SinghCPG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/WangSG22,
author = {Wendong Wang and
Adit D. Singh and
Ujjwal Guin},
title = {A Systematic Bit Selection Method for Robust {SRAM} PUFs},
journal = {J. Electron. Test.},
volume = {38},
number = {3},
pages = {235--246},
year = {2022},
url = {https://doi.org/10.1007/s10836-022-06006-x},
doi = {10.1007/S10836-022-06006-X},
timestamp = {Sat, 10 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/WangSG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/Singh22,
author = {Adit D. Singh},
title = {Understanding Vmin Failures for Improved Testing of Timing Marginalities},
booktitle = {{IEEE} International Test Conference, {ITC} 2022, Anaheim, CA, USA,
September 23-30, 2022},
pages = {372--381},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ITC50671.2022.00046},
doi = {10.1109/ITC50671.2022.00046},
timestamp = {Thu, 05 Jan 2023 13:13:27 +0100},
biburl = {https://dblp.org/rec/conf/itc/Singh22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/ChowdhuryGSA21,
author = {Prattay Chowdhury and
Ujjwal Guin and
Adit D. Singh and
Vishwani D. Agrawal},
title = {Estimating Operational Age of an Integrated Circuit},
journal = {J. Electron. Test.},
volume = {37},
number = {1},
pages = {25--40},
year = {2021},
url = {https://doi.org/10.1007/s10836-021-05927-3},
doi = {10.1007/S10836-021-05927-3},
timestamp = {Tue, 13 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/ChowdhuryGSA21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/DeyatiMSC21,
author = {Sabyasachi Deyati and
Barry J. Muldrey and
Adit D. Singh and
Abhijit Chatterjee},
title = {High Resolution Pulse Propagation Driven Trojan Detection in Digital
Systems},
journal = {J. Electron. Test.},
volume = {37},
number = {1},
pages = {41--63},
year = {2021},
url = {https://doi.org/10.1007/s10836-021-05926-4},
doi = {10.1007/S10836-021-05926-4},
timestamp = {Tue, 13 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/DeyatiMSC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/PandeyLNNSSC21,
author = {Sujay Pandey and
Zhiwei Liao and
Shreyas Nandi and
Suriyaprakash Natarajan and
Arani Sinha and
Adit D. Singh and
Abhijit Chatterjee},
title = {Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay
Impact of Shorts},
booktitle = {39th {IEEE} {VLSI} Test Symposium, {VTS} 2021, San Diego, CA, USA,
April 25-28, 2021},
pages = {1--7},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/VTS50974.2021.9441005},
doi = {10.1109/VTS50974.2021.9441005},
timestamp = {Wed, 09 Jun 2021 08:59:55 +0200},
biburl = {https://dblp.org/rec/conf/vts/PandeyLNNSSC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2103-06656,
author = {Ilia Polian and
Jens Anders and
Steffen Becker and
Paolo Bernardi and
Krishnendu Chakrabarty and
Nourhan Elhamawy and
Matthias Sauer and
Adit D. Singh and
Matteo Sonza Reorda and
Stefan Wagner},
title = {Exploring the Mysteries of System-Level Test},
journal = {CoRR},
volume = {abs/2103.06656},
year = {2021},
url = {https://arxiv.org/abs/2103.06656},
eprinttype = {arXiv},
eprint = {2103.06656},
timestamp = {Tue, 16 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2103-06656.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/WangGS20,
author = {Wendong Wang and
Ujjwal Guin and
Adit D. Singh},
title = {Aging-Resilient SRAM-based True Random Number Generator for Lightweight
Devices},
journal = {J. Electron. Test.},
volume = {36},
number = {3},
pages = {301--311},
year = {2020},
url = {https://doi.org/10.1007/s10836-020-05881-6},
doi = {10.1007/S10836-020-05881-6},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/WangGS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PolianABBCESSRW20,
author = {Ilia Polian and
Jens Anders and
Steffen Becker and
Paolo Bernardi and
Krishnendu Chakrabarty and
Nourhan Elhamawy and
Matthias Sauer and
Adit D. Singh and
Matteo Sonza Reorda and
Stefan Wagner},
title = {Exploring the Mysteries of System-Level Test},
booktitle = {29th {IEEE} Asian Test Symposium, {ATS} 2020, Penang, Malaysia, November
23-26, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ATS49688.2020.9301557},
doi = {10.1109/ATS49688.2020.9301557},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PolianABBCESSRW20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/PandeyLNGNSSC20,
author = {Sujay Pandey and
Zhiwei Liao and
Shreyas Nandi and
Sanya Gupta and
Suriyaprakash Natarajan and
Arani Sinha and
Adit D. Singh and
Abhijit Chatterjee},
title = {{SAT-ATPG} Generated Multi-Pattern Scan Tests for Cell Internal Defects:
Coverage Analysis for Resistive Opens and Shorts},
booktitle = {{IEEE} International Test Conference, {ITC} 2020, Washington, DC,
USA, November 1-6, 2020},
pages = {1--10},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ITC44778.2020.9325240},
doi = {10.1109/ITC44778.2020.9325240},
timestamp = {Mon, 25 Jan 2021 08:44:58 +0100},
biburl = {https://dblp.org/rec/conf/itc/PandeyLNGNSSC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/WangGS20,
author = {Wendong Wang and
Ujjwal Guin and
Adit D. Singh},
title = {A Zero-Cost Detection Approach for Recycled ICs using Scan Architecture},
booktitle = {38th {IEEE} {VLSI} Test Symposium, {VTS} 2020, San Diego, CA, USA,
April 5-8, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/VTS48691.2020.9107583},
doi = {10.1109/VTS48691.2020.9107583},
timestamp = {Thu, 25 Jun 2020 15:32:49 +0200},
biburl = {https://dblp.org/rec/conf/vts/WangGS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/host/GuinWHS19,
author = {Ujjwal Guin and
Wendong Wang and
Charles Harper and
Adit D. Singh},
title = {Detecting Recycled SoCs by Exploiting Aging Induced Biases in Memory
Cells},
booktitle = {{IEEE} International Symposium on Hardware Oriented Security and Trust,
{HOST} 2019, McLean, VA, USA, May 5-10, 2019},
pages = {72--80},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/HST.2019.8741032},
doi = {10.1109/HST.2019.8741032},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/host/GuinWHS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/Singh19,
author = {Adit D. Singh},
title = {An Adaptive Approach to Minimize System Level Tests Targeting Low
Voltage {DVFS} Failures},
booktitle = {{IEEE} International Test Conference, {ITC} 2019, Washington, DC,
USA, November 9-15, 2019},
pages = {1--10},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ITC44170.2019.9000173},
doi = {10.1109/ITC44170.2019.9000173},
timestamp = {Mon, 24 Feb 2020 17:28:46 +0100},
biburl = {https://dblp.org/rec/conf/itc/Singh19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/ChowdhuryGSA19,
author = {Prattay Chowdhury and
Ujjwal Guin and
Adit D. Singh and
Vishwani D. Agrawal},
title = {Two-Pattern {\unicode{8710}}IDDQ Test for Recycled {IC} Detection},
booktitle = {32nd International Conference on {VLSI} Design and 18th International
Conference on Embedded Systems, {VLSID} 2019, Delhi, India, January
5-9, 2019},
pages = {82--87},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSID.2019.00033},
doi = {10.1109/VLSID.2019.00033},
timestamp = {Mon, 14 Nov 2022 15:28:06 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/ChowdhuryGSA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BurchardERSB18,
author = {Jan Burchard and
Dominik Erb and
Sudhakar M. Reddy and
Adit D. Singh and
Bernd Becker},
title = {On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware
Tests for Transistor Stuck-Off Faults in {CMOS} Logic Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {10},
pages = {2152--2165},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2772825},
doi = {10.1109/TCAD.2017.2772825},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/BurchardERSB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuinZS18,
author = {Ujjwal Guin and
Ziqi Zhou and
Adit D. Singh},
title = {Robust Design-for-Security Architecture for Enabling Trust in {IC}
Manufacturing and Test},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {5},
pages = {818--830},
year = {2018},
url = {http://doi.ieeecomputersociety.org/10.1109/TVLSI.2018.2797019},
doi = {10.1109/TVLSI.2018.2797019},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GuinZS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/KraakTHWCCSWK18,
author = {Daniel Kraak and
Mottaqiallah Taouil and
Said Hamdioui and
Pieter Weckx and
Francky Catthoor and
Abhijit Chatterjee and
Adit D. Singh and
Hans{-}Joachim Wunderlich and
Naghmeh Karimi},
title = {Device aging: {A} reliability and security concern},
booktitle = {23rd {IEEE} European Test Symposium, {ETS} 2018, Bremen, Germany,
May 28 - June 1, 2018},
pages = {1--10},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ETS.2018.8400702},
doi = {10.1109/ETS.2018.8400702},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/ets/KraakTHWCCSWK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/latw/WangSGC18,
author = {Wendong Wang and
Adit D. Singh and
Ujjwal Guin and
Abhijit Chatterjee},
title = {Exploiting power supply ramp rate for calibrating cell strength in
{SRAM} PUFs},
booktitle = {19th {IEEE} Latin-American Test Symposium, {LATS} 2018, Sao Paulo,
Brazil, March 12-14, 2018},
pages = {1--6},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/LATW.2018.8349685},
doi = {10.1109/LATW.2018.8349685},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/latw/WangSGC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/GuinSACS18,
author = {Ujjwal Guin and
Adit D. Singh and
Mahabubul Alam and
Janice Canedo and
Anthony Skjellum},
title = {A Secure Low-Cost Edge Device Authentication Scheme for the Internet
of Things},
booktitle = {31st International Conference on {VLSI} Design and 17th International
Conference on Embedded Systems, {VLSID} 2018, Pune, India, January
6-10, 2018},
pages = {85--90},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/VLSID.2018.42},
doi = {10.1109/VLSID.2018.42},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/GuinSACS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/SrivastavaSSS17,
author = {Ankush Srivastava and
Virendra Singh and
Adit D. Singh and
Kewal K. Saluja},
title = {A Reliability-Aware Methodology to Isolate Timing-Critical Paths under
Aging},
journal = {J. Electron. Test.},
volume = {33},
number = {6},
pages = {721--739},
year = {2017},
url = {https://doi.org/10.1007/s10836-017-5692-7},
doi = {10.1007/S10836-017-5692-7},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/SrivastavaSSS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/BurchardESR017,
author = {Jan Burchard and
Dominik Erb and
Adit D. Singh and
Sudhakar M. Reddy and
Bernd Becker},
editor = {David Atienza and
Giorgio Di Natale},
title = {Fast and waveform-accurate hazard-aware SAT-based {TSOF} {ATPG}},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2017, Lausanne, Switzerland, March 27-31, 2017},
pages = {422--427},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/DATE.2017.7927027},
doi = {10.23919/DATE.2017.7927027},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/BurchardESR017.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/0001S17,
author = {Bernd Becker and
Adit D. Singh},
title = {Best paper},
booktitle = {22nd {IEEE} European Test Symposium, {ETS} 2017, Limassol, Cyprus,
May 22-26, 2017},
pages = {1},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ETS.2017.7968207},
doi = {10.1109/ETS.2017.7968207},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/ets/0001S17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/SrivastavaSSS17,
author = {Ankush Srivastava and
Adit D. Singh and
Virendra Singh and
Kewal K. Saluja},
title = {Exploiting path delay test generation to develop better {TDF} tests
for small delay defects},
booktitle = {{IEEE} International Test Conference, {ITC} 2017, Fort Worth, TX,
USA, October 31 - Nov. 2, 2017},
pages = {1--10},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/TEST.2017.8242072},
doi = {10.1109/TEST.2017.8242072},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/itc/SrivastavaSSS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/latw/SrivastavaSSS17,
author = {Ankush Srivastava and
Virendra Singh and
Adit D. Singh and
Kewal K. Saluja},
title = {Identifying high variability speed-limiting paths under aging},
booktitle = {18th {IEEE} Latin American Test Symposium, {LATS} 2017, Bogot{\'{a}},
Colombia, March 13-15, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/LATW.2017.7906757},
doi = {10.1109/LATW.2017.7906757},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/latw/SrivastavaSSS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/BurchardERS017,
author = {Jan Burchard and
Dominik Erb and
Sudhakar M. Reddy and
Adit D. Singh and
Bernd Becker},
title = {Efficient SAT-based generation of hazard-activated {TSOF} tests},
booktitle = {35th {IEEE} {VLSI} Test Symposium, {VTS} 2017, Las Vegas, NV, USA,
April 9-12, 2017},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/VTS.2017.7928943},
doi = {10.1109/VTS.2017.7928943},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/BurchardERS017.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/GuinZS17,
author = {Ujjwal Guin and
Ziqi Zhou and
Adit D. Singh},
title = {A novel design-for-security {(DFS)} architecture to prevent unauthorized
{IC} overproduction},
booktitle = {35th {IEEE} {VLSI} Test Symposium, {VTS} 2017, Las Vegas, NV, USA,
April 9-12, 2017},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/VTS.2017.7928946},
doi = {10.1109/VTS.2017.7928946},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/GuinZS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/PandeyDSC16,
author = {Sujay Pandey and
Sabyasachi Deyati and
Adit D. Singh and
Abhijit Chatterjee},
title = {Noise-Resilient {SRAM} Physically Unclonable Function Design for Security},
booktitle = {25th {IEEE} Asian Test Symposium, {ATS} 2016, Hiroshima, Japan, November
21-24, 2016},
pages = {55--60},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ATS.2016.65},
doi = {10.1109/ATS.2016.65},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/PandeyDSC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/Singh16,
author = {Adit D. Singh},
title = {Cell Aware and stuck-open tests},
booktitle = {21th {IEEE} European Test Symposium, {ETS} 2016, Amsterdam, Netherlands,
May 23-27, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ETS.2016.7519316},
doi = {10.1109/ETS.2016.7519316},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/ets/Singh16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/Singh16,
author = {Adit D. Singh},
title = {Adaptive Test Methods for High {IC} Quality and Reliability},
booktitle = {29th International Conference on {VLSI} Design and 15th International
Conference on Embedded Systems, {VLSID} 2016, Kolkata, India, January
4-8, 2016},
pages = {21--22},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/VLSID.2016.137},
doi = {10.1109/VLSID.2016.137},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/Singh16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/SinghSS15,
author = {Virendra Singh and
Adit D. Singh and
Kewal K. Saluja},
title = {A Methodology for Identifying High Timing Variability Paths in Complex
Designs},
booktitle = {24th {IEEE} Asian Test Symposium, {ATS} 2015, Mumbai, India, November
22-25, 2015},
pages = {115--120},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/ATS.2015.27},
doi = {10.1109/ATS.2015.27},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/SinghSS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/DeyatiMSC15,
author = {Sabyasachi Deyati and
Barry John Muldrey and
Adit D. Singh and
Abhijit Chatterjee},
title = {Challenge Engineering and Design of Analog Push Pull Amplifier Based
Physically Unclonable Function for Hardware Security},
booktitle = {24th {IEEE} Asian Test Symposium, {ATS} 2015, Mumbai, India, November
22-25, 2015},
pages = {127--132},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/ATS.2015.29},
doi = {10.1109/ATS.2015.29},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/DeyatiMSC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/latw/Singh15,
author = {Adit D. Singh},
title = {Scan based two-pattern tests: should they target opens instead of
TDFs?},
booktitle = {16th Latin-American Test Symposium, {LATS} 2015, Puerto Vallarta,
Mexico, March 25-27, 2015},
pages = {1--2},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/LATW.2015.7102526},
doi = {10.1109/LATW.2015.7102526},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/latw/Singh15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/Singh15,
author = {Adit D. Singh},
title = {Embedded Tutorial {ET1:} Better-than-Worst-Case Timing Designs},
booktitle = {28th International Conference on {VLSI} Design, {VLSID} 2015, Bangalore,
India, January 3-7, 2015},
pages = {19--20},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/VLSID.2015.118},
doi = {10.1109/VLSID.2015.118},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/Singh15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/WangS15,
author = {Yu Wang and
Adit D. Singh},
title = {An Efficient Transition Detector Exploiting Charge Sharing},
booktitle = {28th International Conference on {VLSI} Design, {VLSID} 2015, Bangalore,
India, January 3-7, 2015},
pages = {298--303},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/VLSID.2015.57},
doi = {10.1109/VLSID.2015.57},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/WangS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/BarraganLABSS15,
author = {Manuel J. Barrag{\'{a}}n and
Gildas L{\'{e}}ger and
Florence Aza{\"{\i}}s and
Ronald D. Blanton and
Adit D. Singh and
Stephen Sunter},
title = {Special session: Hot topics: Statistical test methods},
booktitle = {33rd {IEEE} {VLSI} Test Symposium, {VTS} 2015, Napa, CA, USA, April
27-29, 2015},
pages = {1--2},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/VTS.2015.7116265},
doi = {10.1109/VTS.2015.7116265},
timestamp = {Wed, 28 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vts/BarraganLABSS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/HanS15,
author = {Chao Han and
Adit D. Singh},
title = {Testing cross wire opens within complex gates},
booktitle = {33rd {IEEE} {VLSI} Test Symposium, {VTS} 2015, Napa, CA, USA, April
27-29, 2015},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/VTS.2015.7116301},
doi = {10.1109/VTS.2015.7116301},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/HanS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/DeyatiMSC14,
author = {Sabyasachi Deyati and
Barry John Muldrey and
Adit D. Singh and
Abhijit Chatterjee},
title = {High Resolution Pulse Propagation Driven Trojan Detection in Digital
Logic: Optimization Algorithms and Infrastructure},
booktitle = {23rd {IEEE} Asian Test Symposium, {ATS} 2014, Hangzhou, China, November
16-19, 2014},
pages = {200--205},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/ATS.2014.45},
doi = {10.1109/ATS.2014.45},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/DeyatiMSC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/ZouHS14,
author = {Jie Zou and
Chao Han and
Adit D. Singh},
title = {Timing Evaluation Tests for Scan Enable Signals with Application to
{TDF} Testing},
booktitle = {23rd {IEEE} Asian Test Symposium, {ATS} 2014, Hangzhou, China, November
16-19, 2014},
pages = {281--286},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/ATS.2014.59},
doi = {10.1109/ATS.2014.59},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/ZouHS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/PolianJS14,
author = {Ilia Polian and
Jie Jiang and
Adit D. Singh},
editor = {Giorgio Di Natale},
title = {Detection conditions for errors in self-adaptive better-than-worst-case
designs},
booktitle = {19th {IEEE} European Test Symposium, {ETS} 2014, Paderborn, Germany,
May 26-30, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ETS.2014.6847794},
doi = {10.1109/ETS.2014.6847794},
timestamp = {Thu, 11 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ets/PolianJS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/Singh14,
author = {Adit D. Singh},
editor = {Giorgio Di Natale},
title = {Error detection and recovery in better-than-worst-case timing designs},
booktitle = {19th {IEEE} European Test Symposium, {ETS} 2014, Paderborn, Germany,
May 26-30, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ETS.2014.6847811},
doi = {10.1109/ETS.2014.6847811},
timestamp = {Mon, 22 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ets/Singh14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/HanS14,
author = {Chao Han and
Adit D. Singh},
title = {On the testing of hazard activated open defects},
booktitle = {2014 International Test Conference, {ITC} 2014, Seattle, WA, USA,
October 20-23, 2014},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/TEST.2014.7035277},
doi = {10.1109/TEST.2014.7035277},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/HanS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/NatarajanKBCS14,
author = {Jayaram Natarajan and
Sahil Kapoor and
Debesh Bhatta and
Abhijit Chatterjee and
Adit D. Singh},
title = {Timing Variation Adaptive Pipeline Design: Using Probabilistic Activity
Completion Sensing with Backup Error Resilience},
booktitle = {2014 27th International Conference on {VLSI} Design, {VLSID} 2014,
and 2014 13th International Conference on Embedded Systems, Mumbai,
India, January 5-9, 2014},
pages = {122--127},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/VLSID.2014.28},
doi = {10.1109/VLSID.2014.28},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/NatarajanKBCS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/UppuUSP14,
author = {Ravi Kanth Uppu and
Ravi Tej Uppu and
Adit D. Singh and
Ilia Polian},
title = {Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths},
booktitle = {2014 27th International Conference on {VLSI} Design, {VLSID} 2014,
and 2014 13th International Conference on Embedded Systems, Mumbai,
India, January 5-9, 2014},
pages = {133--138},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/VLSID.2014.30},
doi = {10.1109/VLSID.2014.30},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/UppuUSP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/HanS14,
author = {Chao Han and
Adit D. Singh},
title = {Improving {CMOS} open defect coverage using hazard activated tests},
booktitle = {32nd {IEEE} {VLSI} Test Symposium, {VTS} 2014, Napa, CA, USA, April
13-17, 2014},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/VTS.2014.6818740},
doi = {10.1109/VTS.2014.6818740},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/HanS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/HanS13,
author = {Chao Han and
Adit D. Singh},
title = {Hazard Initialized {LOC} Tests for {TDF} Undetectable {CMOS} Open
Defects},
booktitle = {22nd Asian Test Symposium, {ATS} 2013, Yilan County, Taiwan, November
18-21, 2013},
pages = {189--194},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/ATS.2013.43},
doi = {10.1109/ATS.2013.43},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/HanS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/ManhaeveHSPAA13,
author = {Hans A. R. Manhaeve and
Pete Harrod and
Adit D. Singh and
Chintan Patel and
Ralf Arnolc and
Davide Appello},
title = {Current testing: Dead or alive?},
booktitle = {18th {IEEE} European Test Symposium, {ETS} 2013, Avignon, France,
May 27-30, 2013},
pages = {1},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/ETS.2013.6569367},
doi = {10.1109/ETS.2013.6569367},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ets/ManhaeveHSPAA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RajskiPSCNGG13,
author = {Janusz Rajski and
Miodrag Potkonjak and
Adit D. Singh and
Abhijit Chatterjee and
Zain Navabi and
Matthew R. Guthaus and
Sezer G{\"{o}}ren},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates
to transistors},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673230},
doi = {10.1109/VLSI-SOC.2013.6673230},
timestamp = {Tue, 16 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/RajskiPSCNGG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/UppuUSC13,
author = {Ravi Tej Uppu and
Ravi Kanth Uppu and
Adit D. Singh and
Abhijit Chatterjee},
title = {A High Throughput Multiplier Design Exploiting Input Based Statistical
Distribution in Completion Delays},
booktitle = {26th International Conference on {VLSI} Design and 12th International
Conference on Embedded Systems, Pune, India, January 5-10, 2013},
pages = {109--114},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/VLSID.2013.172},
doi = {10.1109/VLSID.2013.172},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/UppuUSC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/DworakBFHKMPSX13,
author = {Jennifer Dworak and
Ronald Shawn Blanton and
Masahiro Fujita and
Kazumi Hatayama and
Naghmeh Karimi and
Michail Maniatakos and
Antonis M. Paschalis and
Adit D. Singh and
Tian Xia},
title = {Special session 4B: Elevator talks},
booktitle = {31st {IEEE} {VLSI} Test Symposium, {VTS} 2013, Berkeley, CA, USA,
April 29 - May 2, 2013},
pages = {1},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/VTS.2013.6548899},
doi = {10.1109/VTS.2013.6548899},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/DworakBFHKMPSX13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vdat/2013,
editor = {Manoj Singh Gaur and
Mark Zwolinski and
Vijay Laxmi and
Dharmendar Boolchandani and
Virendra Singh and
Adit D. Singh},
title = {{VLSI} Design and Test, 17th International Symposium, {VDAT} 2013,
Jaipur, India, July 27-30, 2013, Revised Selected Papers},
series = {Communications in Computer and Information Science},
volume = {382},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-3-642-42024-5},
doi = {10.1007/978-3-642-42024-5},
isbn = {978-3-642-42023-8},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vdat/2013.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/ShayanSSF12,
author = {Mohammed Shayan and
Virendra Singh and
Adit D. Singh and
Masahiro Fujita},
title = {{SEU} tolerant robust memory cell design},
booktitle = {18th {IEEE} International On-Line Testing Symposium, {IOLTS} 2012,
Sitges, Spain, June 27-29, 2012},
pages = {13--18},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/IOLTS.2012.6313834},
doi = {10.1109/IOLTS.2012.6313834},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iolts/ShayanSSF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ShayanSSF12,
author = {Mohammed Shayan and
Virendra Singh and
Adit D. Singh and
Masahiro Fujita},
editor = {Hafizur Rahaman and
Sanatan Chattopadhyay and
Santanu Chattopadhyay},
title = {{SEU} Tolerant Robust Latch Design},
booktitle = {Progress in {VLSI} Design and Test - 16th International Symposium,
{VDAT} 2012, Shibpur, India, July 1-4, 2012. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {7373},
pages = {223--232},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-31494-0\_26},
doi = {10.1007/978-3-642-31494-0\_26},
timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
biburl = {https://dblp.org/rec/conf/vdat/ShayanSSF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/QianHS12,
author = {Xi Qian and
Chao Han and
Adit D. Singh},
title = {Detection of gate-oxide defects with timing tests at reduced power
supply},
booktitle = {30th {IEEE} {VLSI} Test Symposium, {VTS} 2012, Maui, Hawaii, USA,
23-26 April 2012},
pages = {120--126},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/VTS.2012.6231090},
doi = {10.1109/VTS.2012.6231090},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vts/QianHS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/RazzaqSS11,
author = {Mohammed Abdul Razzaq and
Virendra Singh and
Adit D. Singh},
title = {{SSTKR:} Secure and Testable Scan Design through Test Key Randomization},
booktitle = {Proceedings of the 20th {IEEE} Asian Test Symposium, {ATS} 2011, New
Delhi, India, November 20-23, 2011},
pages = {60--65},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ATS.2011.85},
doi = {10.1109/ATS.2011.85},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/RazzaqSS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/NatarajanWCS11,
author = {Jayaram Natarajan and
Joshua W. Wells and
Abhijit Chatterjee and
Adit D. Singh},
title = {Distributed Comparison Test Driven Multiprocessor Speed-Tuning: Targeting
Performance Gains under Extreme Process Variations},
booktitle = {Proceedings of the 20th {IEEE} Asian Test Symposium, {ATS} 2011, New
Delhi, India, November 20-23, 2011},
pages = {154--160},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ATS.2011.84},
doi = {10.1109/ATS.2011.84},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/NatarajanWCS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/QianSC11,
author = {Xi Qian and
Adit D. Singh and
Abhijit Chatterjee},
title = {Diagnosing Multiple Slow Gates for Performance Tuning in the Face
of Extreme Process Variations},
booktitle = {Proceedings of the 20th {IEEE} Asian Test Symposium, {ATS} 2011, New
Delhi, India, November 20-23, 2011},
pages = {303--310},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ATS.2011.73},
doi = {10.1109/ATS.2011.73},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/QianSC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/MishraFS11,
author = {Kautalya Mishra and
Ahmed Faraz and
Adit D. Singh},
title = {Path Delay Tuning for Performance Gain in the Face of Random Manufacturing
Variations},
booktitle = {{VLSI} Design 2011: 24th International Conference on {VLSI} Design,
{IIT} Madras, Chennai, India, 2-7 January 2011},
pages = {382--388},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/VLSID.2011.35},
doi = {10.1109/VLSID.2011.35},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/MishraFS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AshoueiCS10,
author = {Maryam Ashouei and
Abhijit Chatterjee and
Adit D. Singh},
title = {Post-Manufacture Tuning for Nano-CMOS Yield Recovery Using Reconfigurable
Logic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {18},
number = {4},
pages = {675--679},
year = {2010},
url = {https://doi.org/10.1109/TVLSI.2009.2014559},
doi = {10.1109/TVLSI.2009.2014559},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AshoueiCS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/GadamsettiS10,
author = {Balapradeep Gadamsetti and
Adit D. Singh},
title = {Current Sensing Completion Detection for high speed and area efficient
arithmetic},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS} 2010,
Kuala Lumpur, Malaysia, December 6-9, 2010},
pages = {240--243},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/APCCAS.2010.5775014},
doi = {10.1109/APCCAS.2010.5775014},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/apccas/GadamsettiS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/QianS10,
author = {Xi Qian and
Adit D. Singh},
title = {Distinguishing Resistive Small Delay Defects from Random Parameter
Variations},
booktitle = {Proceedings of the 19th {IEEE} Asian Test Symposium, {ATS} 2010, 1-4
December 2010, Shanghai, China},
pages = {325--330},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/ATS.2010.62},
doi = {10.1109/ATS.2010.62},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/QianS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/MishraSSSCS10,
author = {Amit Mishra and
Nidhi Sinha and
Satdev and
Virendra Singh and
Sreejit Chakravarty and
Adit D. Singh},
title = {Modified Scan Flip-Flop for Low Power Testing},
booktitle = {Proceedings of the 19th {IEEE} Asian Test Symposium, {ATS} 2010, 1-4
December 2010, Shanghai, China},
pages = {367--370},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/ATS.2010.69},
doi = {10.1109/ATS.2010.69},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/MishraSSSCS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/MarinissenSGECNBAP10,
author = {Erik Jan Marinissen and
Adit D. Singh and
Dan Glotter and
Marco Esposito and
John M. Carulli Jr. and
Amit Nahar and
Kenneth M. Butler and
Davide Appello and
Chris Portelli},
editor = {Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller and
Enrico Macii},
title = {Adapting to adaptive testing},
booktitle = {Design, Automation and Test in Europe, {DATE} 2010, Dresden, Germany,
March 8-12, 2010},
pages = {556--561},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DATE.2010.5457143},
doi = {10.1109/DATE.2010.5457143},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/MarinissenSGECNBAP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/AdigaASSS10,
author = {Raghavendra Adiga and
Gandhi Arpit and
Virendra Singh and
Kewal K. Saluja and
Adit D. Singh},
title = {Modified T-Flip-Flop based scan cell for {RAS}},
booktitle = {15th European Test Symposium, {ETS} 2010, Prague, Czech Republic,
May 24-28, 2010},
pages = {113--118},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/ETSYM.2010.5512773},
doi = {10.1109/ETSYM.2010.5512773},
timestamp = {Tue, 28 Apr 2020 11:43:44 +0200},
biburl = {https://dblp.org/rec/conf/ets/AdigaASSS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/AbhishekKSSS10,
author = {A. Abhishek and
Amanulla Khan and
Virendra Singh and
Kewal K. Saluja and
Adit D. Singh},
title = {Test application time minimization for {RAS} using basis optimization
of column decoder},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2010), May
30 - June 2, 2010, Paris, France},
pages = {2614--2617},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISCAS.2010.5537094},
doi = {10.1109/ISCAS.2010.5537094},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/AbhishekKSSS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/AdigaASSFS10,
author = {Raghavendra Adiga and
Gandhi Arpit and
Virendra Singh and
Kewal K. Saluja and
Hideo Fujiwara and
Adit D. Singh},
title = {On Minimization of Test Application Time for {RAS}},
booktitle = {{VLSI} Design 2010: 23rd International Conference on {VLSI} Design,
9th International Conference on Embedded Systems, Bangalore, India,
3-7 January 2010},
pages = {393--398},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/VLSI.Design.2010.61},
doi = {10.1109/VLSI.DESIGN.2010.61},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/AdigaASSFS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/SinghHQ10,
author = {Adit D. Singh and
Chao Han and
Xi Qian},
title = {An output compression scheme for handling X-states from over-clocked
delay tests},
booktitle = {28th {IEEE} {VLSI} Test Symposium, {VTS} 2010, April 19-22, 2010,
Santa Cruz, California, {USA}},
pages = {57--62},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/VTS.2010.5469617},
doi = {10.1109/VTS.2010.5469617},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vts/SinghHQ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/DeepakRSS09,
author = {K. G. Deepak and
Robinson Reyna and
Virendra Singh and
Adit D. Singh},
title = {Leveraging Partially Enhanced Scan for Improved Observability in Delay
Fault Testing},
booktitle = {Proceedings of the Eighteentgh Asian Test Symposium, {ATS} 2009, 23-26
November 2009, Taichung, Taiwan},
pages = {237--240},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ATS.2009.78},
doi = {10.1109/ATS.2009.78},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/DeepakRSS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/Singh09,
author = {Adit D. Singh},
editor = {Dimitris Gizopoulos and
Susumu Horiguchi and
Spyros Tragoudas and
Mohammad Tehranipoor},
title = {A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap
{CMOS}},
booktitle = {24th {IEEE} International Symposium on Defect and Fault Tolerance
in {VLSI} Systems, {DFT} 2009, Chicago, Illinois, USA, October 7-9,
2009},
pages = {422--422},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/DFT.2009.65},
doi = {10.1109/DFT.2009.65},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/Singh09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/ChatterjeeASMKP09,
author = {Abhijit Chatterjee and
Jacob A. Abraham and
Adit D. Singh and
Elie Maricau and
Rakesh Kumar and
Christos A. Papachristou},
title = {Panel: Realistic low power design: Let errors occur and correct them
later or mitigate errors via design guardbanding and process control?},
booktitle = {15th {IEEE} International On-Line Testing Symposium {(IOLTS} 2009),
24-26 June 2009, Sesimbra-Lisbon, Portugal},
pages = {129},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/IOLTS.2009.5195994},
doi = {10.1109/IOLTS.2009.5195994},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iolts/ChatterjeeASMKP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/MenonSA09,
author = {Sreekumar Menon and
Adit D. Singh and
Vishwani D. Agrawal},
title = {Output Hazard-Free Transition Delay Fault Test Generation},
booktitle = {27th {IEEE} {VLSI} Test Symposium, {VTS} 2009, May 3-7, 2009, Santa
Cruz, California, {USA}},
pages = {97--102},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/VTS.2009.40},
doi = {10.1109/VTS.2009.40},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/MenonSA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/Singh08,
author = {Adit D. Singh},
editor = {Douglas Young and
Nur A. Touba},
title = {Scan Based Testing of Dual/Multi Core Processors for Small Delay Defects},
booktitle = {2008 {IEEE} International Test Conference, {ITC} 2008, Santa Clara,
California, USA, October 26-31, 2008},
pages = {1--8},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/TEST.2008.4700563},
doi = {10.1109/TEST.2008.4700563},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/Singh08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/Singh08,
author = {Adit D. Singh},
title = {Scan Delay Testing of Nanometer SoCs},
booktitle = {21st International Conference on {VLSI} Design {(VLSI} Design 2008),
4-8 January 2008, Hyderabad, India},
pages = {13},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/VLSI.2008.134},
doi = {10.1109/VLSI.2008.134},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/Singh08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/AshoueiSC08,
author = {Maryam Ashouei and
Adit D. Singh and
Abhijit Chatterjee},
title = {Reconfiguring {CMOS} as Pseudo {N/PMOS} for Defect Tolerance in Nano-Scale
{CMOS}},
booktitle = {21st International Conference on {VLSI} Design {(VLSI} Design 2008),
4-8 January 2008, Hyderabad, India},
pages = {27--32},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/VLSI.2008.104},
doi = {10.1109/VLSI.2008.104},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/AshoueiSC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/XuS07,
author = {Gefu Xu and
Adit D. Singh},
title = {Scan cell design for launch-on-shift delay tests with slow scan enable},
journal = {{IET} Comput. Digit. Tech.},
volume = {1},
number = {3},
pages = {213--219},
year = {2007},
url = {https://doi.org/10.1049/iet-cdt:20060142},
doi = {10.1049/IET-CDT:20060142},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/XuS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/XuS07,
author = {Gefu Xu and
Adit D. Singh},
title = {Flip-flop Selection to Maximize {TDF} Coverage with Partial Enhanced
Scan},
booktitle = {16th Asian Test Symposium, {ATS} 2007, Beijing, China, October 8-11,
2007},
pages = {335--340},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ATS.2007.96},
doi = {10.1109/ATS.2007.96},
timestamp = {Wed, 09 Nov 2022 21:30:34 +0100},
biburl = {https://dblp.org/rec/conf/ats/XuS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/XuS07,
author = {Gefu Xu and
Adit D. Singh},
editor = {Jill Sibert and
Janusz Rajski},
title = {Achieving high transition delay fault coverage with partial {DTSFF}
scan chains},
booktitle = {2007 {IEEE} International Test Conference, {ITC} 2007, Santa Clara,
California, USA, October 21-26, 2007},
pages = {1--9},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/TEST.2007.4437608},
doi = {10.1109/TEST.2007.4437608},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/XuS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/AshoueiNCSD07,
author = {Maryam Ashouei and
Muhammad Mudassar Nisar and
Abhijit Chatterjee and
Adit D. Singh and
Abdulkadir Utku Diril},
title = {Probabilistic Self-Adaptation of Nanoscale {CMOS} Circuits: Yield
Maximization under Increased Intra-Die Variations},
booktitle = {20th International Conference on {VLSI} Design {(VLSI} Design 2007),
Sixth International Conference on Embedded Systems {(ICES} 2007),
6-10 January 2007, Bangalore, India},
pages = {711--716},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/VLSID.2007.130},
doi = {10.1109/VLSID.2007.130},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/AshoueiNCSD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/XuS07,
author = {Gefu Xu and
Adit D. Singh},
title = {Delay Test Scan Flip-Flop: {DFT} for High Coverage Delay Testing},
booktitle = {20th International Conference on {VLSI} Design {(VLSI} Design 2007),
Sixth International Conference on Embedded Systems {(ICES} 2007),
6-10 January 2007, Bangalore, India},
pages = {763--768},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/VLSID.2007.61},
doi = {10.1109/VLSID.2007.61},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/XuS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/BarnettGPS06,
author = {Thomas S. Barnett and
Matt Grady and
Kathleen G. Purdy and
Adit D. Singh},
title = {Combining Negative Binomial and Weibull Distributions for Yield and
Reliability Prediction},
journal = {{IEEE} Des. Test Comput.},
volume = {23},
number = {2},
pages = {110--116},
year = {2006},
url = {https://doi.org/10.1109/MDT.2006.38},
doi = {10.1109/MDT.2006.38},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/BarnettGPS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/Al-HashimiGSS06,
author = {Bashir M. Al{-}Hashimi and
Dimitris Gizopoulos and
Manoj Sachdev and
Adit D. Singh},
title = {New {JETTA} Editors, 2006},
journal = {J. Electron. Test.},
volume = {22},
number = {1},
pages = {9--10},
year = {2006},
url = {https://doi.org/10.1007/s10836-006-6905-7},
doi = {10.1007/S10836-006-6905-7},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/Al-HashimiGSS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/XuanSC06,
author = {Xiangdong Xuan and
Adit D. Singh and
Abhijit Chatterjee},
title = {Lifetime Prediction and Design-for-Reliability of {IC} Interconnections
with Electromigration Induced Degradation in the Presence of Manufacturing
Defects},
journal = {J. Electron. Test.},
volume = {22},
number = {4-6},
pages = {471--482},
year = {2006},
url = {https://doi.org/10.1007/s10836-006-9498-2},
doi = {10.1007/S10836-006-9498-2},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/XuanSC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DhillonDCS06,
author = {Yuvraj Singh Dhillon and
Abdulkadir Utku Diril and
Abhijit Chatterjee and
Adit D. Singh},
title = {Analysis and Optimization of Nanometer {CMOS} Circuits for Soft-Error
Tolerance},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {14},
number = {5},
pages = {514--524},
year = {2006},
url = {https://doi.org/10.1109/TVLSI.2006.876104},
doi = {10.1109/TVLSI.2006.876104},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DhillonDCS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YanS06,
author = {Haihua Yan and
Adit D. Singh},
title = {A New Delay Test Based on Delay Defect Detection Within Slack Intervals
{(DDSI)}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {14},
number = {11},
pages = {1216--1226},
year = {2006},
url = {https://doi.org/10.1109/TVLSI.2006.886415},
doi = {10.1109/TVLSI.2006.886415},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YanS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/XuS06,
author = {Gefu Xu and
Adit D. Singh},
title = {Low Cost Launch-on-Shift Delay Test with Slow Scan Enable},
booktitle = {11th European Test Symposium, {ETS} 2006, Southhampton, UK, May 21-24,
2006},
pages = {9--14},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ETS.2006.29},
doi = {10.1109/ETS.2006.29},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ets/XuS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/AshoueiCSDM06,
author = {Maryam Ashouei and
Abhijit Chatterjee and
Adit D. Singh and
Vivek De and
T. M. Mak},
title = {Statistical Estimation of Correlated Leakage Power Variation and Its
Application to Leakage-Aware Design},
booktitle = {19th International Conference on {VLSI} Design {(VLSI} Design 2006),
3-7 January 2006, Hyderabad, India},
pages = {606--612},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/VLSID.2006.152},
doi = {10.1109/VLSID.2006.152},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/AshoueiCSDM06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/SinghX06,
author = {Adit D. Singh and
Gefu Xu},
title = {Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based
Delay Testing},
booktitle = {24th {IEEE} {VLSI} Test Symposium {(VTS} 2006), 30 April - 4 May 2006,
Berkeley, California, {USA}},
pages = {349--357},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/VTS.2006.53},
doi = {10.1109/VTS.2006.53},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/SinghX06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/DirilDCS05,
author = {Abdulkadir Utku Diril and
Yuvraj Singh Dhillon and
Abhijit Chatterjee and
Adit D. Singh},
title = {Pseudo Dual Supply Voltage Domino Logic Design},
journal = {J. Low Power Electron.},
volume = {1},
number = {2},
pages = {145--152},
year = {2005},
url = {https://doi.org/10.1166/jolpe.2005.021},
doi = {10.1166/JOLPE.2005.021},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jolpe/DirilDCS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DirilDCS05,
author = {Abdulkadir Utku Diril and
Yuvraj Singh Dhillon and
Abhijit Chatterjee and
Adit D. Singh},
title = {Level-shifter free design of low power dual supply voltage {CMOS}
circuits using dual threshold voltages},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {9},
pages = {1103--1107},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.857149},
doi = {10.1109/TVLSI.2005.857149},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DirilDCS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/DirilDCS05,
author = {Abdulkadir Utku Diril and
Yuvraj Singh Dhillon and
Abhijit Chatterjee and
Adit D. Singh},
editor = {Tingao Tang},
title = {Low-power domino circuits using {NMOS} pull-up on off-critical paths},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {533--538},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1120956},
doi = {10.1145/1120725.1120956},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/DirilDCS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/Singh05,
author = {Adit D. Singh},
title = {{T2:} Statistical Methods for {VLSI} Test and Burn-in Optimization},
booktitle = {14th Asian Test Symposium {(ATS} 2005), 18-21 December 2005, Calcutta,
India},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ATS.2005.104},
doi = {10.1109/ATS.2005.104},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/Singh05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/YanSX05,
author = {Haihua Yan and
Adit D. Singh and
Gefu Xu},
title = {Delay Defect Characterization Using Low Voltage Test},
booktitle = {14th Asian Test Symposium {(ATS} 2005), 18-21 December 2005, Calcutta,
India},
pages = {8--13},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ATS.2005.45},
doi = {10.1109/ATS.2005.45},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/YanSX05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/AshoueiCSD05,
author = {Maryam Ashouei and
Abhijit Chatterjee and
Adit D. Singh and
Vivek De},
title = {A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization
in Nanometer {CMOS}},
booktitle = {23rd International Conference on Computer Design {(ICCD} 2005), 2-5
October 2005, San Jose, CA, {USA}},
pages = {567--573},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICCD.2005.6},
doi = {10.1109/ICCD.2005.6},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/AshoueiCSD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/YanXS05,
author = {Haihua Yan and
Gefu Xu and
Adit D. Singh},
title = {Low Voltage Test in Place of Fast Clock in {DDSI} Delay Test},
booktitle = {6th International Symposium on Quality of Electronic Design {(ISQED}
2005), 21-23 March 2005, San Jose, CA, {USA}},
pages = {316--320},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISQED.2005.75},
doi = {10.1109/ISQED.2005.75},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/YanXS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/Singh05,
author = {Adit D. Singh},
title = {A self-timed structural test methodology for timing anomalies due
to defects and process variations},
booktitle = {Proceedings 2005 {IEEE} International Test Conference, {ITC} 2005,
Austin, TX, USA, November 8-10, 2005},
pages = {7},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/TEST.2005.1583964},
doi = {10.1109/TEST.2005.1583964},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/Singh05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/MudlapurAS05,
author = {Anand S. Mudlapur and
Vishwani D. Agrawal and
Adit D. Singh},
title = {A random access scans architecture to reduce hardware overhead},
booktitle = {Proceedings 2005 {IEEE} International Test Conference, {ITC} 2005,
Austin, TX, USA, November 8-10, 2005},
pages = {9},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/TEST.2005.1583993},
doi = {10.1109/TEST.2005.1583993},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/MudlapurAS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/YanS05,
author = {Haihua Yan and
Adit D. Singh},
title = {A Delay Test to Differentiate Resistive Interconnect Faults from Weak
Transistor Defects},
booktitle = {18th International Conference on {VLSI} Design {(VLSI} Design 2005),
with the 4th International Conference on Embedded Systems Design,
3-7 January 2005, Kolkata, India},
pages = {47--52},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICVD.2005.9},
doi = {10.1109/ICVD.2005.9},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/YanS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/DirilDCS05,
author = {Abdulkadir Utku Diril and
Yuvraj Singh Dhillon and
Abhijit Chatterjee and
Adit D. Singh},
title = {Level-Shifter Free Design of Low Power Dual Supply Voltage {CMOS}
Circuits Using Dual Threshold Voltages},
booktitle = {18th International Conference on {VLSI} Design {(VLSI} Design 2005),
with the 4th International Conference on Embedded Systems Design,
3-7 January 2005, Kolkata, India},
pages = {159--164},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICVD.2005.115},
doi = {10.1109/ICVD.2005.115},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/DirilDCS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/DirilDCS05,
author = {Abdulkadir Utku Diril and
Yuvraj Singh Dhillon and
Abhijit Chatterjee and
Adit D. Singh},
title = {Design of Adaptive Nanometer Digital Systems for Effective Control
of Soft Error Tolerance},
booktitle = {23rd {IEEE} {VLSI} Test Symposium {(VTS} 2005), 1-5 May 2005, Palm
Springs, CA, {USA}},
pages = {298--303},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/VTS.2005.40},
doi = {10.1109/VTS.2005.40},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/DirilDCS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/YanS04,
author = {Haihua Yan and
Adit D. Singh},
title = {Reduce Yield Loss in Delay Defect Detection in Slack Interval},
booktitle = {13th Asian Test Symposium {(ATS} 2004), 15-17 November 2004, Kenting,
Taiwan},
pages = {372--377},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ATS.2004.74},
doi = {10.1109/ATS.2004.74},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/YanS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ets/XuanCS04,
author = {Xiangdong Xuan and
Abhijit Chatterjee and
Adit D. Singh},
title = {Application of local design-for-reliability techniques for reducing
wear-out degradation of {CMOS} combinational logic circuits},
booktitle = {9th European Test Symposium, {ETS} 2004, Ajaccio, France, May 23-26,
2004},
pages = {24--29},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ETSYM.2004.1347593},
doi = {10.1109/ETSYM.2004.1347593},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ets/XuanCS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/DhillonDCS04,
author = {Yuvraj Singh Dhillon and
Abdulkadir Utku Diril and
Abhijit Chatterjee and
Adit D. Singh},
title = {Sizing {CMOS} Circuits for Increased Transient Error Tolerance},
booktitle = {10th {IEEE} International On-Line Testing Symposium {(IOLTS} 2004),
12-14 July 2004, Funchal, Madeira Island, Portugal},
pages = {11--16},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.ieeecomputersociety.org/10.1109/IOLTS.2004.44},
doi = {10.1109/IOLTS.2004.44},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iolts/DhillonDCS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/YanS04,
author = {Haihua Yan and
Adit D. Singh},
title = {Evaluating the Effectiveness of Detecting Delay Defects in the Slack
Interval: {A} Simulation Study},
booktitle = {Proceedings 2004 International Test Conference {(ITC} 2004), October
26-28, 2004, Charlotte, NC, {USA}},
pages = {242--251},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/TEST.2004.1386958},
doi = {10.1109/TEST.2004.1386958},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/YanS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/DhillonDCS04,
author = {Yuvraj Singh Dhillon and
Abdulkadir Utku Diril and
Abhijit Chatterjee and
Adit D. Singh},
editor = {Edna Natividade da Silva Barros and
Fl{\'{a}}vio Rech Wagner and
Luigi Carro and
Franz{-}Josef Rammig},
title = {Low-power dual V\({}_{\mbox{th}}\) pseudo dual V\({}_{\mbox{dd}}\)
domino circuits},
booktitle = {Proceedings of the 17th Annual Symposium on Integrated Circuits and
Systems Design, {SBCCI} 2004, Pernambuco, Brazil, September 7-11,
2004},
pages = {273--277},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/1016568.1016640},
doi = {10.1145/1016568.1016640},
timestamp = {Fri, 03 Jun 2022 10:53:26 +0200},
biburl = {https://dblp.org/rec/conf/sbcci/DhillonDCS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/SinghSGS03,
author = {Adit D. Singh and
Markus Seuring and
Michael G{\"{o}}ssel and
Egor S. Sogomonyan},
title = {Multimode scan: Test per clock {BIST} for {IP} cores},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {8},
number = {4},
pages = {491--505},
year = {2003},
url = {https://doi.org/10.1145/944027.944033},
doi = {10.1145/944027.944033},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/SinghSGS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tr/BarnettSN03,
author = {Thomas S. Barnett and
Adit D. Singh and
Victor P. Nelson},
title = {Extending integrated-circuit yield-models to estimate early-life reliability},
journal = {{IEEE} Trans. Reliab.},
volume = {52},
number = {3},
pages = {296--300},
year = {2003},
url = {https://doi.org/10.1109/TR.2003.816418},
doi = {10.1109/TR.2003.816418},
timestamp = {Thu, 09 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tr/BarnettSN03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/XuanCSKC03,
author = {Xiangdong Xuan and
Abhijit Chatterjee and
Adit D. Singh and
Namsoo P. Kim and
Mark T. Chisa},
title = {{IC} Reliability Simulator {ARET} and Its Application in Design-for-Reliability},
booktitle = {12th Asian Test Symposium {(ATS} 2003), 17-19 November 2003, Xian,
China},
pages = {18--23},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ATS.2003.1250775},
doi = {10.1109/ATS.2003.1250775},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/XuanCSKC03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/Singh03,
author = {Adit D. Singh},
title = {Integrating Yield, Test and Reliability: "Statistical Models
with Applications to Test and Burn-in Optimization"},
booktitle = {4th International Symposium on Quality of Electronic Design {(ISQED}
2003), 24-26 March 2003, San Jose, CA, {USA}},
pages = {7},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.ieeecomputersociety.org/10.1109/ISQED.2003.10006},
doi = {10.1109/ISQED.2003.10006},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/Singh03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/BarnettS03,
author = {Thomas S. Barnett and
Adit D. Singh},
title = {Relating Yield Models to Burn-In Fall-Out in Time},
booktitle = {Proceedings 2003 International Test Conference {(ITC} 2003), Breaking
Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte,
NC, {USA}},
pages = {77--84},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/TEST.2003.1270827},
doi = {10.1109/TEST.2003.1270827},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/BarnettS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/YanS03,
author = {Haihua Yan and
Adit D. Singh},
title = {Experiments in Detecting Delay Faults using Multiple Higher Frequency
Clocks and Results from Neighboring Die},
booktitle = {Proceedings 2003 International Test Conference {(ITC} 2003), Breaking
Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte,
NC, {USA}},
pages = {105--111},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/TEST.2003.1270830},
doi = {10.1109/TEST.2003.1270830},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/YanS03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/Singh03,
author = {Adit D. Singh},
title = {Should Nanometer Circuits be Periodically Tested in the Field?},
booktitle = {Proceedings 2003 International Test Conference {(ITC} 2003), Breaking
Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte,
NC, {USA}},
pages = {1280},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/TEST.2003.1271120},
doi = {10.1109/TEST.2003.1271120},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/Singh03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/BarnettGPS02,
author = {Thomas S. Barnett and
Matt Grady and
Kathleen G. Purdy and
Adit D. Singh},
title = {Redundancy Implications for Early-Life Reliability: Experimental Verification
of an Integrated Yield-Reliability Model},
booktitle = {Proceedings {IEEE} International Test Conference 2002, Baltimore,
MD, USA, October 7-10, 2002},
pages = {693--699},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/TEST.2002.1041821},
doi = {10.1109/TEST.2002.1041821},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/BarnettGPS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/GoesselSS02,
author = {Michael G{\"{o}}ssel and
Egor S. Sogomonyan and
Adit D. Singh},
title = {Scan-Path with Directly Duplicated and Inverted Duplicated Registers},
booktitle = {20th {IEEE} {VLSI} Test Symposium {(VTS} 2002), Without Testing It's
a Gamble, 28 April - 2 May 2002, Monterey, CA, {USA}},
pages = {47--52},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/VTS.2002.1011110},
doi = {10.1109/VTS.2002.1011110},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/GoesselSS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/BarnettSGP02,
author = {Thomas S. Barnett and
Adit D. Singh and
Matt Grady and
Kathleen G. Purdy},
title = {Yield-Reliability Modeling: Experimental Verification and Application
to Burn-In Reduction},
booktitle = {20th {IEEE} {VLSI} Test Symposium {(VTS} 2002), Without Testing It's
a Gamble, 28 April - 2 May 2002, Monterey, CA, {USA}},
pages = {75--80},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/VTS.2002.1011114},
doi = {10.1109/VTS.2002.1011114},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/BarnettSGP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/BarnettSN01,
author = {Thomas S. Barnett and
Adit D. Singh and
Victor P. Nelson},
title = {Yield-Reliability Modeling for Fault Tolerant Integrated Circuits},
booktitle = {16th {IEEE} International Symposium on Defect and Fault-Tolerance
in {VLSI} Systems {(DFT} 2001), 24-26 October 2001, San Francisco,
CA, USA, Proceedings},
pages = {29--38},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/DFTVS.2001.966749},
doi = {10.1109/DFTVS.2001.966749},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/BarnettSN01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/BarnettSN01,
author = {Thomas S. Barnett and
Adit D. Singh and
Victor P. Nelson},
title = {Estimating burn-in fall-out for redundant memory},
booktitle = {Proceedings {IEEE} International Test Conference 2001, Baltimore,
MD, USA, 30 October - 1 November 2001},
pages = {340--347},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/TEST.2001.966650},
doi = {10.1109/TEST.2001.966650},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/BarnettSN01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/SogomonyanMRGS01,
author = {Egor S. Sogomonyan and
Andrej A. Morosov and
Jan Rzeha and
Michael G{\"{o}}ssel and
Adit D. Singh},
title = {Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed
Debugging},
booktitle = {19th {IEEE} {VLSI} Test Symposium {(VTS} 2001), Test and Diagnosis
in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA,
{USA}},
pages = {184--189},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/VTS.2001.923437},
doi = {10.1109/VTS.2001.923437},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/SogomonyanMRGS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/BarnettSN01,
author = {Thomas S. Barnett and
Adit D. Singh and
Victor P. Nelson},
title = {Burn-In Failures and Local Region Yield: An Integrated Yield-Reliability
Model},
booktitle = {19th {IEEE} {VLSI} Test Symposium {(VTS} 2001), Test and Diagnosis
in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA,
{USA}},
pages = {326--332},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/VTS.2001.923457},
doi = {10.1109/VTS.2001.923457},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/BarnettSN01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/SogomonyanSG99,
author = {Egor S. Sogomonyan and
Adit D. Singh and
Michael G{\"{o}}ssel},
title = {A Multi-Mode Scannable Memory Element for High Test Application Efficiency
and Delay Testing},
journal = {J. Electron. Test.},
volume = {15},
number = {1-2},
pages = {87--96},
year = {1999},
url = {https://doi.org/10.1023/A:1008328101088},
doi = {10.1023/A:1008328101088},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/SogomonyanSG99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/LakinS99,
author = {David R. Lakin II and
Adit D. Singh},
title = {Exploiting defect clustering to screen bare die for infant mortality
failures: an experimental study},
booktitle = {Proceedings {IEEE} International Test Conference 1999, Atlantic City,
NJ, USA, 27-30 September 1999},
pages = {23--30},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/TEST.1999.805610},
doi = {10.1109/TEST.1999.805610},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/LakinS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/SinghSGS99,
author = {Adit D. Singh and
Egor S. Sogomonyan and
Michael G{\"{o}}ssel and
Markus Seuring},
title = {Testability evaluation of sequential designs incorporating the multi-mode
scannable memory element},
booktitle = {Proceedings {IEEE} International Test Conference 1999, Atlantic City,
NJ, USA, 27-30 September 1999},
pages = {286--293},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/TEST.1999.805642},
doi = {10.1109/TEST.1999.805642},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/SinghSGS99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KnightSN98,
author = {Christopher G. Knight and
Adit D. Singh and
Victor P. Nelson},
title = {An {IDDQ} sensor for concurrent timing error detection},
journal = {{IEEE} J. Solid State Circuits},
volume = {33},
number = {10},
pages = {1545--1550},
year = {1998},
url = {https://doi.org/10.1109/4.720401},
doi = {10.1109/4.720401},
timestamp = {Tue, 05 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KnightSN98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/SinghLSN98,
author = {Adit D. Singh and
David R. Lakin II and
Gaurav Sinha and
Phil Nigh},
title = {Binning for {IC} Quality: Experimental Studies on the {SEMATECH} Data},
booktitle = {13th International Symposium on Defect and Fault-Tolerance in {VLSI}
Systems {(DFT} '98), 2-4 November 1998, Austin, TX, USA, Proceedings},
pages = {4--10},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/DFTVS.1998.732145},
doi = {10.1109/DFTVS.1998.732145},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/SinghLSN98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/SogomonyanSG98,
author = {Egor S. Sogomonyan and
Adit D. Singh and
Michael G{\"{o}}ssel},
title = {A Multi-Mode Scannable Memory Element for High Test Application Efficiency
and Delay Testing},
booktitle = {16th {IEEE} {VLSI} Test Symposium {(VTS} '98), 28 April - 1 May 1998,
Princeton, NJ, {USA}},
pages = {324--331},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/VTEST.1998.670886},
doi = {10.1109/VTEST.1998.670886},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/SogomonyanSG98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/WeberS97,
author = {Walter W. Weber and
Adit D. Singh},
title = {Incorporating \emph{I}\({}_{\mbox{DDQ}}\) Testing with {BIST} for
Improved Coverage: An Experimental Study},
journal = {J. Electron. Test.},
volume = {11},
number = {2},
pages = {147--156},
year = {1997},
url = {https://doi.org/10.1023/A:1008218422533},
doi = {10.1023/A:1008218422533},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/WeberS97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/HurstS97,
author = {Jason P. Hurst and
Adit D. Singh},
title = {A differential built-in current sensor design for high-speed {IDDQ}
testing},
journal = {{IEEE} J. Solid State Circuits},
volume = {32},
number = {1},
pages = {122--125},
year = {1997},
url = {https://doi.org/10.1109/4.553192},
doi = {10.1109/4.553192},
timestamp = {Thu, 07 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/HurstS97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/KnightSN97,
author = {Christopher G. Knight and
Adit D. Singh and
Victor P. Nelson},
title = {An {IDDQ} Sensor for Concurrent Timing Error Detection},
booktitle = {1997 Workshop on Defect and Fault-Tolerance in {VLSI} Systems {(DFT}
'97), 20-22 October 1997, Paris, France},
pages = {281--289},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/DFTVS.1997.628335},
doi = {10.1109/DFTVS.1997.628335},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/KnightSN97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/SinghNK97,
author = {Adit D. Singh and
Phil Nigh and
C. Mani Krishna},
title = {Screening for Known Good Die {(KGD)} Based on Defect Clustering: An
Experimental Study},
booktitle = {Proceedings {IEEE} International Test Conference 1997, Washington,
DC, USA, November 3-5, 1997},
pages = {362--369},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/TEST.1997.639638},
doi = {10.1109/TEST.1997.639638},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/SinghNK97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/SinghK96,
author = {Adit D. Singh and
C. Mani Krishna},
title = {On the Effect of Defect Clustering on Test Transparency and {IC} Test
Optimization},
journal = {{IEEE} Trans. Computers},
volume = {45},
number = {6},
pages = {753--757},
year = {1996},
url = {https://doi.org/10.1109/12.506431},
doi = {10.1109/12.506431},
timestamp = {Sat, 10 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/SinghK96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/LeeYS95,
author = {Jae Young Lee and
Hee Yong Youn and
Adit D. Singh},
title = {Adaptive Unanimous Voting {(UV)} Scheme for Distributed Self-Diagnosis},
journal = {{IEEE} Trans. Computers},
volume = {44},
number = {5},
pages = {730--735},
year = {1995},
url = {https://doi.org/10.1109/12.381964},
doi = {10.1109/12.381964},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/LeeYS95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dft/Singh95,
author = {Adit D. Singh},
title = {{ADTS:} an array defect-tolerance scheme for wafer scale gate arrays},
booktitle = {1995 {IEEE} International Symposium on Defect and Fault Tolerance
in {VLSI} and Nanotechnology Systems, {DFT} 1995, Lafayette, LA, USA,
November 13-15, 1995},
pages = {126--136},
publisher = {{IEEE} Computer Society},
year = {1995},
url = {https://doi.org/10.1109/DFTVS.1995.476945},
doi = {10.1109/DFTVS.1995.476945},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dft/Singh95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/SinghRW95,
author = {Adit D. Singh and
Haroon Rasheed and
Walter W. Weber},
title = {I\({}_{\mbox{DDQ}}\) Testing of {CMOS} Opens: An Experimental Study},
booktitle = {Proceedings {IEEE} International Test Conference 1995, Driving Down
the Cost of Test, Washington, DC, USA, October 21-25, 1995},
pages = {479--489},
publisher = {{IEEE} Computer Society},
year = {1995},
url = {https://doi.org/10.1109/TEST.1995.529875},
doi = {10.1109/TEST.1995.529875},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/SinghRW95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/HurstS95,
author = {Jason P. Hurst and
Adit D. Singh},
title = {A differential built-in current sensor design for high speed {IDDQ}
testing},
booktitle = {8th International Conference on {VLSI} Design {(VLSI} Design 1995),
4-7 January 1995, New Delhi, India},
pages = {419--423},
publisher = {{IEEE} Computer Society},
year = {1995},
url = {https://doi.org/10.1109/ICVD.1995.512150},
doi = {10.1109/ICVD.1995.512150},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/HurstS95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/WeberS95,
author = {Walter W. Weber and
Adit D. Singh},
title = {An experimental evaluation of the differential {BICS} for I\({}_{\mbox{DDQ}}\)
testing},
booktitle = {13th {IEEE} {VLSI} Test Symposium (VTS'95), April 30 - May 3, 1995,
Princeton, New Jersey, {USA}},
pages = {472--485},
publisher = {{IEEE} Computer Society},
year = {1995},
url = {https://doi.org/10.1109/VTEST.1995.512677},
doi = {10.1109/VTEST.1995.512677},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/WeberS95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/SinghH94,
author = {Adit D. Singh and
Jason P. Hurst},
title = {Incorporating {IDDQ} testing in {BIST:} improved coverage through
test diversity},
booktitle = {12th {IEEE} {VLSI} Test Symposium (VTS'94), April 25-28, 1994, Cherry
Hill, New Jersey, {USA}},
pages = {374--379},
publisher = {{IEEE} Computer Society},
year = {1994},
url = {https://doi.org/10.1109/VTEST.1994.292286},
doi = {10.1109/VTEST.1994.292286},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/SinghH94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SinghK93,
author = {Adit D. Singh and
C. Mani Krishna},
title = {On optimizing {VLSI} testing for product quality using die-yield prediction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {12},
number = {5},
pages = {695--709},
year = {1993},
url = {https://doi.org/10.1109/43.277614},
doi = {10.1109/43.277614},
timestamp = {Sat, 10 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SinghK93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ftcs/LeeYS93,
author = {Jae Young Lee and
Hee Yong Youn and
Adit D. Singh},
title = {Adaptive Voting for Faulty {(VFF)} Node Scheme for Distributed Self-Diagnosis},
booktitle = {Digest of Papers: FTCS-23, The Twenty-Third Annual International Symposium
on Fault-Tolerant Computing, Toulouse, France, June 22-24, 1993},
pages = {480--489},
publisher = {{IEEE} Computer Society},
year = {1993},
url = {https://doi.org/10.1109/FTCS.1993.627351},
doi = {10.1109/FTCS.1993.627351},
timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
biburl = {https://dblp.org/rec/conf/ftcs/LeeYS93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/SinghK93,
author = {Adit D. Singh and
C. Mani Krishna},
title = {The effect of defect clustering on test transparency and defect levels},
booktitle = {11th {IEEE} {VLSI} Test Symposium (VTS'93), 6 Apr 1993-8 Apr 1993,
Atlantic City, NJ, {USA}},
pages = {99--105},
publisher = {{IEEE} Computer Society},
year = {1993},
url = {https://doi.org/10.1109/VTEST.1993.313301},
doi = {10.1109/VTEST.1993.313301},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/SinghK93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ftcs/SinghK92,
author = {Adit D. Singh and
C. Mani Krishna},
title = {Chip Test Optimization Using Defect Clustering Information},
booktitle = {Digest of Papers: FTCS-22, The Twenty-Second Annual International
Symposium on Fault-Tolerant Computing, Boston, Massachusetts, USA,
July 8-10, 1992},
pages = {366--373},
publisher = {{IEEE} Computer Society},
year = {1992},
url = {https://doi.org/10.1109/FTCS.1992.243564},
doi = {10.1109/FTCS.1992.243564},
timestamp = {Sat, 10 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ftcs/SinghK92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/KrishnaS92,
author = {C. Mani Krishna and
Adit D. Singh},
title = {Analysis of the die test optimization algorithm for negative binomial
yield statistics},
booktitle = {10th {IEEE} {VLSI} Test Symposium (VTS'92), 7-9 Apr 1992, Atlantic
City, NJ, {USA}},
pages = {176--181},
publisher = {{IEEE} Computer Society},
year = {1992},
url = {https://doi.org/10.1109/VTEST.1992.232745},
doi = {10.1109/VTEST.1992.232745},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/KrishnaS92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/SinghY91,
author = {Adit D. Singh and
Hee Yong Youn},
title = {A Modular Fault-Tolerant Binary Tree Architecture with Short Links},
journal = {{IEEE} Trans. Computers},
volume = {40},
number = {7},
pages = {882--890},
year = {1991},
url = {https://doi.org/10.1109/12.83628},
doi = {10.1109/12.83628},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/SinghY91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/SinghK91,
author = {Adit D. Singh and
C. Mani Krishna},
title = {On Optimizing Wafer-Probe Testing for Product Quality Using Die-Yield
Prediction},
booktitle = {Proceedings {IEEE} International Test Conference 1991, Test: Faster,
Better, Sooner, Nashville, TN, USA, October 26-30, 1991},
pages = {228--237},
publisher = {{IEEE} Computer Society},
year = {1991},
url = {https://doi.org/10.1109/TEST.1991.519514},
doi = {10.1109/TEST.1991.519514},
timestamp = {Sat, 10 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/itc/SinghK91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/computer/SinghM90,
author = {Adit D. Singh and
Singaravel Murugesan},
title = {Fault-Tolerant Systems - Guest Editors' Introduction to the Special
Issue},
journal = {Computer},
volume = {23},
number = {7},
pages = {15--17},
year = {1990},
url = {https://doi.org/10.1109/2.56848},
doi = {10.1109/2.56848},
timestamp = {Wed, 12 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/computer/SinghM90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/computer/KorenS90,
author = {Israel Koren and
Adit D. Singh},
title = {Fault Tolerance in {VLSI} Circuits},
journal = {Computer},
volume = {23},
number = {7},
pages = {73--83},
year = {1990},
url = {https://doi.org/10.1109/2.56854},
doi = {10.1109/2.56854},
timestamp = {Wed, 12 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/computer/KorenS90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/MendelsonPS89,
author = {Abraham Mendelson and
Dhiraj K. Pradhan and
Adit D. Singh},
title = {A single cached copy data coherence scheme for multiprocessor systems},
journal = {{SIGARCH} Comput. Archit. News},
volume = {17},
number = {6},
pages = {36--49},
year = {1989},
url = {https://doi.org/10.1145/77254.77257},
doi = {10.1145/77254.77257},
timestamp = {Thu, 08 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sigarch/MendelsonPS89.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/YounS89,
author = {Hee Yong Youn and
Adit D. Singh},
title = {On Implementing Large Binary Tree Architectures in {VLSI} and {WSI}},
journal = {{IEEE} Trans. Computers},
volume = {38},
number = {4},
pages = {526--537},
year = {1989},
url = {https://doi.org/10.1109/12.21145},
doi = {10.1109/12.21145},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/YounS89.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ftcs/KrishnaS89,
author = {C. Mani Krishna and
Adit D. Singh},
title = {Modelling correlated transient failures in fault-tolerant systems},
booktitle = {Proceedings of the Nineteenth International Symposium on Fault-Tolerant
Computing, {FTCS} 1989, Chicago, IL, USA, 21-23 June, 1989},
pages = {374--381},
publisher = {{IEEE} Computer Society},
year = {1989},
url = {https://doi.org/10.1109/FTCS.1989.105595},
doi = {10.1109/FTCS.1989.105595},
timestamp = {Sat, 10 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ftcs/KrishnaS89.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/YounS89,
author = {Hee Yong Youn and
Adit D. Singh},
title = {An efficient channel routing algorithm for defective arrays},
booktitle = {1989 {IEEE} International Conference on Computer-Aided Design, {ICCAD}
1989, Santa Clara, CA, USA, November 5-9, 1989. Digest of Technical
Papers},
pages = {432--435},
publisher = {{IEEE} Computer Society},
year = {1989},
url = {https://doi.org/10.1109/ICCAD.1989.76985},
doi = {10.1109/ICCAD.1989.76985},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/YounS89.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpp/YounS89,
author = {Hee Yong Youn and
Adit D. Singh},
title = {A Near Optimal Adaptive Row Modular Design for Efficiently Reconfiguring
the Processor Array in {VLSI}},
booktitle = {Proceedings of the International Conference on Parallel Processing,
{ICPP} '89, The Pennsylvania State University, University Park, PA,
USA, August 1989. Volume 1: Architecture},
pages = {261--265},
publisher = {Pennsylvania State University Press},
year = {1989},
timestamp = {Mon, 28 Jul 2014 17:06:00 +0200},
biburl = {https://dblp.org/rec/conf/icpp/YounS89.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/Singh88,
author = {Adit D. Singh},
title = {Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme
for Large Area {VLSI} Processor Arrays},
journal = {{IEEE} Trans. Computers},
volume = {37},
number = {11},
pages = {1398--1410},
year = {1988},
url = {https://doi.org/10.1109/12.8705},
doi = {10.1109/12.8705},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/Singh88.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icdcs/YounS88,
author = {Hee Yong Youn and
Adit D. Singh},
title = {Near Optimal Embedding of Binary Tree Architecture in {VLSI}},
booktitle = {Proceedings of the 8th International Conference on Distributed Computing
Systems, San Jose, California, USA, June 13-17, 1988},
pages = {86--93},
publisher = {{IEEE} Computer Society},
year = {1988},
url = {https://doi.org/10.1109/DCS.1988.12503},
doi = {10.1109/DCS.1988.12503},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/icdcs/YounS88.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpp/YounS88,
author = {Hee Yong Youn and
Adit D. Singh},
title = {A Highly Efficient Design for Reconfiguring the Processor Array in
{VLSI}},
booktitle = {Proceedings of the International Conference on Parallel Processing,
{ICPP} '88, The Pennsylvania State University, University Park, PA,
USA, August 1988. Volume 1: Architecture},
pages = {375--382},
publisher = {Pennsylvania State University Press},
year = {1988},
timestamp = {Mon, 28 Jul 2014 17:06:01 +0200},
biburl = {https://dblp.org/rec/conf/icpp/YounS88.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpp/YounS87,
author = {Hee Yong Youn and
Adit D. Singh},
title = {On Area Efficient and Fault Tolerant Tree Embedding In {VLSI}},
booktitle = {International Conference on Parallel Processing, ICPP'87, University
Park, PA, USA, August 1987},
pages = {170--177},
publisher = {Pennsylvania State University Press},
year = {1987},
timestamp = {Mon, 28 Jul 2014 17:06:01 +0200},
biburl = {https://dblp.org/rec/conf/icpp/YounS87.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/SinghGA81,
author = {Adit D. Singh and
F. Gail Gray and
James R. Armstrong},
title = {Tree Structured Sequential Multiple-Valued Logic Design from Universal
Modules},
journal = {{IEEE} Trans. Computers},
volume = {30},
number = {9},
pages = {671--674},
year = {1981},
url = {https://doi.org/10.1109/TC.1981.1675866},
doi = {10.1109/TC.1981.1675866},
timestamp = {Sun, 08 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/SinghGA81.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/SinghA78,
author = {Adit D. Singh and
James R. Armstrong},
title = {A simultaneous, radix four, {I2L} multiplier mechanized via repeated
addition},
booktitle = {Proceedings of the eighth international symposium on Multiple-valued
logic, {MVL} 1978, Rosemont, Illinois, USA, 1978},
pages = {114--121},
publisher = {{IEEE} Computer Society Press},
year = {1978},
url = {http://dl.acm.org/citation.cfm?id=804195},
timestamp = {Mon, 09 Aug 2021 11:27:20 +0200},
biburl = {https://dblp.org/rec/conf/ismvl/SinghA78.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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