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ORCIDBibTeX records: Arvind K. Sharma
@article{DBLP:journals/ci/SyedUNAS23,
author = {Mohammad Haider Syed and
Kamal Upreti and
Mohammad Shahnawaz Nasir and
Mohammad Shabbir Alam and
Arvind Kumar Sharma},
title = {Addressing image and Poisson noise deconvolution problem using deep
learning approaches},
journal = {Comput. Intell.},
volume = {39},
number = {4},
pages = {577--591},
year = {2023},
url = {https://doi.org/10.1111/coin.12510},
doi = {10.1111/COIN.12510},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ci/SyedUNAS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AcharyaSMSDSMRD23,
author = {Lomash Chandra Acharya and
Arvind Kumar Sharma and
Neeraj Mishra and
Khoirom Johnson Singh and
Mahipal Dargupally and
Nayakanti Sai Shabarish and
Ajoy Mandal and
Venkatraman Ramakrishnan and
Sudeb Dasgupta and
Anand Bulusu},
title = {Aging-Aware Timing Model of {CMOS} Inverter: Path Level Timing Performance
and Its Impact on the Logical Effort},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {42},
number = {8},
pages = {2657--2663},
year = {2023},
url = {https://doi.org/10.1109/TCAD.2022.3231173},
doi = {10.1109/TCAD.2022.3231173},
timestamp = {Sat, 05 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AcharyaSMSDSMRD23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KarmokarSPMHS23,
author = {Nibedita Karmokar and
Arvind K. Sharma and
Jitesh Poojary and
Meghna Madhusudan and
Ramesh Harjani and
Sachin S. Sapatnekar},
title = {Constructive Placement and Routing for Common-Centroid Capacitor Arrays
in Binary-Weighted and Split DACs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {42},
number = {9},
pages = {2782--2795},
year = {2023},
url = {https://doi.org/10.1109/TCAD.2023.3238880},
doi = {10.1109/TCAD.2023.3238880},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KarmokarSPMHS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KunalDMPSXBHHS23,
author = {Kishor Kunal and
Tonmoy Dhar and
Meghna Madhusudan and
Jitesh Poojary and
Arvind K. Sharma and
Wenbin Xu and
Steven M. Burns and
Jiang Hu and
Ramesh Harjani and
Sachin S. Sapatnekar},
title = {GNN-Based Hierarchical Annotation for Analog Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {42},
number = {9},
pages = {2801--2814},
year = {2023},
url = {https://doi.org/10.1109/TCAD.2023.3236269},
doi = {10.1109/TCAD.2023.3236269},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KunalDMPSXBHHS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LiLMSSHH23,
author = {Yaguang Li and
Yishuang Lin and
Meghna Madhusudan and
Arvind K. Sharma and
Sachin S. Sapatnekar and
Ramesh Harjani and
Jiang Hu},
title = {Performance-driven Wire Sizing for Analog Integrated Circuits},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {28},
number = {2},
pages = {19:1--19:23},
year = {2023},
url = {https://doi.org/10.1145/3559542},
doi = {10.1145/3559542},
timestamp = {Wed, 17 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/LiLMSSHH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/GopalakrishnanMSPYHBS23,
author = {Ramprasath Srinivasa Gopalakrishnan and
Meghna Madhusudan and
Arvind K. Sharma and
Jitesh Poojary and
Soner Yaldiz and
Ramesh Harjani and
Steven M. Burns and
Sachin S. Sapatnekar},
title = {A Generalized Methodology for Well Island Generation and Well-tap
Insertion in Analog/Mixed-signal Layouts},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {28},
number = {5},
pages = {69:1--69:25},
year = {2023},
url = {https://doi.org/10.1145/3580477},
doi = {10.1145/3580477},
timestamp = {Fri, 27 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/GopalakrishnanMSPYHBS23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KamineniSHSC23,
author = {Sumanth Kamineni and
Arvind K. Sharma and
Ramesh Harjani and
Sachin S. Sapatnekar and
Benton H. Calhoun},
title = {AuxcellGen: {A} Framework for Autonomous Generation of Analog and
Memory Unit Cells},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2023, Antwerp, Belgium, April 17-19, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/DATE56975.2023.10137270},
doi = {10.23919/DATE56975.2023.10137270},
timestamp = {Wed, 07 Jun 2023 22:08:03 +0200},
biburl = {https://dblp.org/rec/conf/date/KamineniSHSC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/essderc/MadhusudanPSSKSH23,
author = {Meghna Madhusudan and
Jitesh Poojary and
Arvind K. Sharma and
Ramprasath S and
Kishor Kunal and
Sachin S. Sapatnekar and
Ramesh Harjani},
title = {Understanding Distance-Dependent Variations for Analog Circuits in
a FinFET Technology},
booktitle = {53rd {IEEE} European Solid-State Device Research Conference, {ESSDERC}
2023, Lisbon, Portugal, September 11-14, 2023},
pages = {69--72},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ESSDERC59256.2023.10268572},
doi = {10.1109/ESSDERC59256.2023.10268572},
timestamp = {Wed, 18 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/essderc/MadhusudanPSSKSH23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/smacd/AcharyaKSGSMDSRMDB23,
author = {Lomash Chandra Acharya and
Anubhav Kumar and
Khoirom Johnson Singh and
Neha Gupta and
Nayakanti Sai Shabarish and
Neeraj Mishra and
Mahipal Dargupally and
Arvind Kumar Sharma and
Venkatraman Ramakrishnan and
Ajoy Mandal and
Sudeb Dasgupta and
Anand Bulusu},
title = {Beyond {SPICE} Simulation: {A} Novel Variability-Aware {STA} Methodology
for Digital Timing Closure},
booktitle = {19th International Conference on Synthesis, Modeling, Analysis and
Simulation Methods and Applications to Circuit Design, {SMACD} 2023,
Funchal, Portugal, July 3-5, 2023},
pages = {1--4},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/SMACD58065.2023.10192158},
doi = {10.1109/SMACD58065.2023.10192158},
timestamp = {Wed, 09 Aug 2023 16:10:31 +0200},
biburl = {https://dblp.org/rec/conf/smacd/AcharyaKSGSMDSRMDB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KarmokarMSHLS22,
author = {Nibedita Karmokar and
Meghna Madhusudan and
Arvind K. Sharma and
Ramesh Harjani and
Mark Po{-}Hung Lin and
Sachin S. Sapatnekar},
title = {Common-Centroid Layout for Active and Passive Devices: {A} Review
and the Road Ahead},
booktitle = {27th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2022, Taipei, Taiwan, January 17-20, 2022},
pages = {114--121},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ASP-DAC52403.2022.9712576},
doi = {10.1109/ASP-DAC52403.2022.9712576},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/KarmokarMSHLS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KarmokarSPMHS22,
author = {Nibedita Karmokar and
Arvind K. Sharma and
Jitesh Poojary and
Meghna Madhusudan and
Ramesh Harjani and
Sachin S. Sapatnekar},
editor = {Cristiana Bolchini and
Ingrid Verbauwhede and
Ioana Vatajelu},
title = {Constructive Common-Centroid Placement and Routing for Binary-Weighted
Capacitor Arrays},
booktitle = {2022 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2022, Antwerp, Belgium, March 14-23, 2022},
pages = {166--171},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.23919/DATE54114.2022.9774640},
doi = {10.23919/DATE54114.2022.9774640},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/KarmokarSPMHS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/SMSPYHBS22,
author = {Ramprasath S and
Meghna Madhusudan and
Arvind K. Sharma and
Jitesh Poojary and
Soner Yaldiz and
Ramesh Harjani and
Steven M. Burns and
Sachin S. Sapatnekar},
editor = {Laleh Behjat and
Stephen Yang},
title = {Analog/Mixed-Signal Layout Optimization using Optimal Well Taps},
booktitle = {{ISPD} 2022: International Symposium on Physical Design, Virtual Event,
Canada, March 27 - 30, 2022},
pages = {159--166},
publisher = {{ACM}},
year = {2022},
url = {https://doi.org/10.1145/3505170.3506728},
doi = {10.1145/3505170.3506728},
timestamp = {Wed, 18 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ispd/SMSPYHBS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/DharKLMPSXBHHKM21,
author = {Tonmoy Dhar and
Kishor Kunal and
Yaguang Li and
Meghna Madhusudan and
Jitesh Poojary and
Arvind K. Sharma and
Wenbin Xu and
Steven M. Burns and
Ramesh Harjani and
Jiang Hu and
Desmond A. Kirkpatrick and
Parijat Mukherjee and
Soner Yaldiz and
Sachin S. Sapatnekar},
title = {{ALIGN:} {A} System for Automating Analog Layout},
journal = {{IEEE} Des. Test},
volume = {38},
number = {2},
pages = {8--18},
year = {2021},
url = {https://doi.org/10.1109/MDAT.2020.3042177},
doi = {10.1109/MDAT.2020.3042177},
timestamp = {Thu, 29 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/DharKLMPSXBHHKM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/itiis/KshirsagarMTNSS21,
author = {Pravin Kshirsagar and
Hariprasath Manoharan and
Vineet Tirth and
Mohd Naved and
Ahmad Tasnim Siddiqui and
Arvind K. Sharma},
title = {Automation Monitoring With Sensors For Detecting Covid Using Backpropagation
Algorithm},
journal = {{KSII} Trans. Internet Inf. Syst.},
volume = {15},
number = {7},
pages = {2414--2433},
year = {2021},
url = {https://doi.org/10.3837/tiis.2021.07.007},
doi = {10.3837/TIIS.2021.07.007},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/itiis/KshirsagarMTNSS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/DharPLKMSMHHS21,
author = {Tonmoy Dhar and
Jitesh Poojary and
Yaguang Li and
Kishor Kunal and
Meghna Madhusudan and
Arvind K. Sharma and
Susmita Dey Manasi and
Jiang Hu and
Ramesh Harjani and
Sachin S. Sapatnekar},
title = {Fast and Efficient Constraint Evaluation of Analog Layout Using Machine
Learning Models},
booktitle = {{ASPDAC} '21: 26th Asia and South Pacific Design Automation Conference,
Tokyo, Japan, January 18-21, 2021},
pages = {158--163},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3394885.3431547},
doi = {10.1145/3394885.3431547},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/DharPLKMSMHHS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SharmaMBMYHS21,
author = {Arvind K. Sharma and
Meghna Madhusudan and
Steven M. Burns and
Parijat Mukherjee and
Soner Yaldiz and
Ramesh Harjani and
Sachin S. Sapatnekar},
title = {Common-Centroid Layouts for Analog Circuits: Advantages and Limitations},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2021, Grenoble, France, February 1-5, 2021},
pages = {1224--1229},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/DATE51398.2021.9474244},
doi = {10.23919/DATE51398.2021.9474244},
timestamp = {Wed, 21 Jul 2021 10:04:34 +0200},
biburl = {https://dblp.org/rec/conf/date/SharmaMBMYHS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/MadhusudanSLHSH21,
author = {Meghna Madhusudan and
Arvind K. Sharma and
Yaguang Li and
Jiang Hu and
Sachin S. Sapatnekar and
Ramesh Hajiani},
title = {Analog Layout Generation using Optimized Primitives},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2021, Grenoble, France, February 1-5, 2021},
pages = {1234--1239},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/DATE51398.2021.9474010},
doi = {10.23919/DATE51398.2021.9474010},
timestamp = {Wed, 21 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/MadhusudanSLHSH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LiuSMHSZRLHSSHL21,
author = {Juzheng Liu and
Shiyu Su and
Meghna Madhusudan and
Mohsen Hassanpourghadi and
Samuel Saunders and
Qiaochu Zhang and
Rezwan A. Rasul and
Yaguang Li and
Jiang Hu and
Arvind Kumar Sharma and
Sachin S. Sapatnekar and
Ramesh Harjani and
Anthony Levi and
Sandeep Gupta and
Mike Shuo{-}Wei Chen},
title = {From Specification to Silicon: Towards Analog/Mixed-Signal Design
Automation using Surrogate {NN} Models with Transfer Learning},
booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
2021, Munich, Germany, November 1-4, 2021},
pages = {1--9},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICCAD51958.2021.9643445},
doi = {10.1109/ICCAD51958.2021.9643445},
timestamp = {Thu, 21 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/LiuSMHSZRLHSSHL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/SharmaMBYMHS21,
author = {Arvind K. Sharma and
Meghna Madhusudan and
Steven M. Burns and
Soner Yaldiz and
Parijat Mukherjee and
Ramesh Harjani and
Sachin S. Sapatnekar},
title = {Performance-Aware Common-Centroid Placement and Routing of Transistor
Arrays in Analog Circuits},
booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
2021, Munich, Germany, November 1-4, 2021},
pages = {1--9},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICCAD51958.2021.9643532},
doi = {10.1109/ICCAD51958.2021.9643532},
timestamp = {Tue, 28 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/SharmaMBYMHS21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/DharKLLMPSBHHMY21,
author = {Tonmoy Dhar and
Kishor Kunal and
Yaguang Li and
Yishuang Lin and
Meghna Madhusudan and
Jitesh Poojary and
Arvind K. Sharma and
Steven M. Burns and
Ramesh Harjani and
Jiang Hu and
Parijat Mukherjee and
Soner Yaldiz and
Sachin S. Sapatnekar},
editor = {Jens Lienig and
Laleh Behjat and
Stephen Yang},
title = {Machine Learning Techniques in Analog Layout Automation},
booktitle = {{ISPD} '21: International Symposium on Physical Design, Virtual Event,
USA, March 22-24, 2021},
pages = {71--72},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3439706.3446896},
doi = {10.1145/3439706.3446896},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ispd/DharKLLMPSBHHMY21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/AcharyaSRMDB21,
author = {Lomash Chandra Acharya and
Arvind Kumar Sharma and
Venkatraman Ramakrishnan and
Ajoy Mandal and
Sudeb Dasgupta and
Anand Bulusu},
title = {Variation Aware Timing Model of {CMOS} Inverter for an Efficient {ECSM}
Characterization},
booktitle = {22nd International Symposium on Quality Electronic Design, {ISQED}
2021, Santa Clara, CA, USA, April 7-9, 2021},
pages = {251--256},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISQED51717.2021.9424341},
doi = {10.1109/ISQED51717.2021.9424341},
timestamp = {Fri, 28 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isqed/AcharyaSRMDB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mlcad/LiLMSSHH21,
author = {Yaguang Li and
Yishuang Lin and
Meghna Madhusudan and
Arvind K. Sharma and
Sachin S. Sapatnekar and
Ramesh Harjani and
Jiang Hu},
title = {A Circuit Attention Network-Based Actor-Critic Learning Approach to
Robust Analog Transistor Sizing},
booktitle = {3rd {ACM/IEEE} Workshop on Machine Learning for CAD, {MLCAD} 2021,
Raleigh, NC, USA, August 30 - Sept. 3, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/MLCAD52597.2021.9531156},
doi = {10.1109/MLCAD52597.2021.9531156},
timestamp = {Fri, 17 Sep 2021 14:46:40 +0200},
biburl = {https://dblp.org/rec/conf/mlcad/LiLMSSHH21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KunalDMPSXBHHS20,
author = {Kishor Kunal and
Tonmoy Dhar and
Meghna Madhusudan and
Jitesh Poojary and
Arvind K. Sharma and
Wenbin Xu and
Steven M. Burns and
Jiang Hu and
Ramesh Harjani and
Sachin S. Sapatnekar},
title = {{GANA:} Graph Convolutional Network Based Automated Netlist Annotation
for Analog Circuits},
booktitle = {2020 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2020, Grenoble, France, March 9-13, 2020},
pages = {55--60},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.23919/DATE48585.2020.9116329},
doi = {10.23919/DATE48585.2020.9116329},
timestamp = {Wed, 19 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/KunalDMPSXBHHS20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/DharKLLMPSBHHMY20,
author = {Tonmoy Dhar and
Kishor Kunal and
Yaguang Li and
Yishuang Lin and
Meghna Madhusudan and
Jitesh Poojary and
Arvind K. Sharma and
Steven M. Burns and
Ramesh Harjani and
Jiang Hu and
Parijat Mukherjee and
Soner Yaldiz and
Sachin S. Sapatnekar},
title = {The {ALIGN} Open-Source Analog Layout Generator: v1.0 and Beyond (Invited
talk)},
booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
2020, San Diego, CA, USA, November 2-5, 2020},
pages = {54:1--54:2},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1145/3400302.3415784},
doi = {10.1145/3400302.3415784},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/DharKLLMPSBHHMY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LiLMSXSHH20,
author = {Yaguang Li and
Yishuang Lin and
Meghna Madhusudan and
Arvind K. Sharma and
Wenbin Xu and
Sachin S. Sapatnekar and
Ramesh Harjani and
Jiang Hu},
title = {A Customized Graph Neural Network Model for Guiding Analog {IC} Placement},
booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
2020, San Diego, CA, USA, November 2-5, 2020},
pages = {135:1--135:9},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1145/3400302.3415624},
doi = {10.1145/3400302.3415624},
timestamp = {Mon, 18 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/LiLMSXSHH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/KunalDLMPSXBHHM20,
author = {Kishor Kunal and
Tonmoy Dhar and
Yaguang Li and
Meghna Madhusudan and
Jitesh Poojary and
Arvind K. Sharma and
Wenbin Xu and
Steven M. Burns and
Ramesh Harjani and
Jiang Hu and
Parijat Mukherjee and
Sachin S. Sapatnekar},
editor = {William Swartz and
Jens Lienig},
title = {Learning from Experience: Applying {ML} to Analog Circuit Design},
booktitle = {{ISPD} 2020: International Symposium on Physical Design, Taipei, Taiwan,
March 29 - April 1, 2020, delayed to September 20-23, 2020},
pages = {55},
publisher = {{ACM}},
year = {2020},
url = {https://doi.org/10.1145/3372780.3378172},
doi = {10.1145/3372780.3378172},
timestamp = {Wed, 19 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ispd/KunalDLMPSXBHHM20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/LiLMSXSHH20,
author = {Yaguang Li and
Yishuang Lin and
Meghna Madhusudan and
Arvind K. Sharma and
Wenbin Xu and
Sachin S. Sapatnekar and
Ramesh Harjani and
Jiang Hu},
title = {Exploring a Machine Learning Approach to Performance Driven Analog
{IC} Placement},
booktitle = {2020 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2020,
Limassol, Cyprus, July 6-8, 2020},
pages = {24--29},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISVLSI49217.2020.00015},
doi = {10.1109/ISVLSI49217.2020.00015},
timestamp = {Wed, 12 Aug 2020 14:38:21 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/LiLMSXSHH20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2008-10682,
author = {Tonmoy Dhar and
Kishor Kunal and
Yaguang Li and
Meghna Madhusudan and
Jitesh Poojary and
Arvind K. Sharma and
Wenbin Xu and
Steven M. Burns and
Ramesh Harjani and
Jiang Hu and
Desmond A. Kirkpatrick and
Parijat Mukherjee and
Sachin S. Sapatnekar and
Soner Yaldiz},
title = {{ALIGN:} {A} System for Automating Analog Layout},
journal = {CoRR},
volume = {abs/2008.10682},
year = {2020},
url = {https://arxiv.org/abs/2008.10682},
eprinttype = {arXiv},
eprint = {2008.10682},
timestamp = {Fri, 28 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2008-10682.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/KumarSPB19,
author = {Chaudhry Indra Kumar and
Arvind Kumar Sharma and
Rajendra Partap and
Anand Bulusu},
title = {An energy-efficient variation aware self-correcting latch},
journal = {Microelectron. J.},
volume = {84},
pages = {67--78},
year = {2019},
url = {https://doi.org/10.1016/j.mejo.2018.12.006},
doi = {10.1016/J.MEJO.2018.12.006},
timestamp = {Sat, 22 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/KumarSPB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KumarBSSJB19,
author = {Chaudhry Indra Kumar and
Ishant Bhatia and
Arvind Kumar Sharma and
Deep Sehgal and
H. S. Jatana and
Anand Bulusu},
title = {A Physics-Based Variability-Aware Methodology to Estimate Critical
Charge for Near-Threshold Voltage Latches},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {9},
pages = {2170--2179},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2019.2910825},
doi = {10.1109/TVLSI.2019.2910825},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KumarBSSJB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KunalMSXBHHKS19,
author = {Kishor Kunal and
Meghna Madhusudan and
Arvind K. Sharma and
Wenbin Xu and
Steven M. Burns and
Ramesh Harjani and
Jiang Hu and
Desmond A. Kirkpatrick and
Sachin S. Sapatnekar},
title = {{ALIGN:} Open-Source Analog Layout Automation from the Ground Up},
booktitle = {Proceedings of the 56th Annual Design Automation Conference 2019,
{DAC} 2019, Las Vegas, NV, USA, June 02-06, 2019},
pages = {77},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3316781.3323471},
doi = {10.1145/3316781.3323471},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/KunalMSXBHHKS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/prime/SharmaAB18,
author = {Arvind Kumar Sharma and
Naushad Alam and
Anand Bulusu},
title = {{UTBB} {FD-SOI} Circuit Design using Multifinger Transistors: {A}
Circuit-Device Interaction Perspective},
booktitle = {14th Conference on Ph.D. Research in Microelectronics and Electronics,
{PRIME} 2018, Prague, Czech Republic, July 2-5, 2018},
pages = {57--60},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/PRIME.2018.8430312},
doi = {10.1109/PRIME.2018.8430312},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/prime/SharmaAB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/KaurSAMA16,
author = {Baljit Kaur and
Arvind Kumar Sharma and
Naushad Alam and
S. K. Manhas and
Bulusu Anand},
title = {A variation aware timing model for a 2-input {NAND} gate and its use
in sub-65 nm {CMOS} standard cell characterization},
journal = {Microelectron. J.},
volume = {53},
pages = {45--55},
year = {2016},
url = {https://doi.org/10.1016/j.mejo.2016.03.010},
doi = {10.1016/J.MEJO.2016.03.010},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mj/KaurSAMA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/smacd/KumarSMB16,
author = {Chaudhry Indra Kumar and
Arvind Kumar Sharma and
Sandeep Miryala and
Anand Bulusu},
title = {A novel energy-efficient self-correcting methodology employing {INWE}},
booktitle = {13th International Conference on Synthesis, Modeling, Analysis and
Simulation Methods and Applications to Circuit Design, {SMACD} 2016,
Lisbon, Portugal, June 27-30, 2016},
pages = {1--4},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/SMACD.2016.7520744},
doi = {10.1109/SMACD.2016.7520744},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/smacd/KumarSMB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/smacd/VarmaSA16,
author = {Sayyaparaju Sagar Varma and
Arvind Kumar Sharma and
Bulusu Anand},
title = {An efficient methodology to characterize the {TSPC} flip flop setup
time for static timing analysis},
booktitle = {13th International Conference on Synthesis, Modeling, Analysis and
Simulation Methods and Applications to Circuit Design, {SMACD} 2016,
Lisbon, Portugal, June 27-30, 2016},
pages = {1--4},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/SMACD.2016.7520724},
doi = {10.1109/SMACD.2016.7520724},
timestamp = {Wed, 08 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/smacd/VarmaSA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/SharmaSDA15,
author = {Arvind Kumar Sharma and
Yogendra Sharma and
Sudeb Dasgupta and
Bulusu Anand},
title = {Efficient static D-latch standard cell characterization using a novel
setup time model},
booktitle = {Sixteenth International Symposium on Quality Electronic Design, {ISQED}
2015, Santa Clara, CA, USA, March 2-4, 2015},
pages = {371--378},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISQED.2015.7085454},
doi = {10.1109/ISQED.2015.7085454},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/SharmaSDA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/ChaurasiyaBSKA15,
author = {Yogesh Chaurasiya and
Surabhi Bhargava and
Arvind Kumar Sharma and
Baljit Kaur and
Bulusu Anand},
title = {Timing model for two stage buffer and its application in {ECSM} characterization},
booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
Ahmedabad, India, June 26-29, 2015},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/ISVDAT.2015.7208075},
doi = {10.1109/ISVDAT.2015.7208075},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vdat/ChaurasiyaBSKA15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/SharmaMADB15,
author = {Arvind Kumar Sharma and
Neeraj Mishra and
Naushad Alam and
Sudeb Dasgupta and
Anand Bulusu},
title = {Pre-layout estimation of performance and design of basic analog circuits
in stress enabled technologies},
booktitle = {19th International Symposium on {VLSI} Design and Test, {VDAT} 2015,
Ahmedabad, India, June 26-29, 2015},
pages = {1--6},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/ISVDAT.2015.7208062},
doi = {10.1109/ISVDAT.2015.7208062},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vdat/SharmaMADB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vdat/DalaiKSA14,
author = {Bijay Kumar Dalai and
N. Karnnan and
Arvind Kumar Sharma and
Bulusu Anand},
title = {An empirical delta delay model for highly scaled {CMOS} inverter considering
Well Proximity Effect},
booktitle = {18th International Symposium on {VLSI} Design and Test, {VDAT} 2014,
Coimbatore, India, July 16-18, 2014},
pages = {1--2},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISVDAT.2014.6881062},
doi = {10.1109/ISVDAT.2014.6881062},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/vdat/DalaiKSA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicsyn/VasudevaSK09,
author = {Amol Vasudeva and
Arvind Kumar Sharma and
Ashish Kumar},
editor = {David Al{-}Dabass and
Geetam S. Tomar and
Rajeev Tripathi and
Ajith Abraham},
title = {Saksham: Customizable x86 Based Multi-Core Microprocessor Simulator},
booktitle = {First International Conference on Computational Intelligence, Communication
Systems and Networks, {CICSYN} 2009, Indore, India, 23-25 July, 2009},
pages = {220--225},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/CICSYN.2009.41},
doi = {10.1109/CICSYN.2009.41},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cicsyn/VasudevaSK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/AustSFGTTL06,
author = {Michael V. Aust and
Arvind K. Sharma and
Owen Fordham and
Ronald Grundbacher and
Richard To and
Roger S. Tsai and
Richard Lai},
title = {A 2.8-W Q-Band High-Efficiency Power Amplifier},
journal = {{IEEE} J. Solid State Circuits},
volume = {41},
number = {10},
pages = {2241--2247},
year = {2006},
url = {https://doi.org/10.1109/JSSC.2006.878102},
doi = {10.1109/JSSC.2006.878102},
timestamp = {Fri, 15 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/AustSFGTTL06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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