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ORCIDBibTeX records: Jonathan Rose
@inproceedings{DBLP:conf/eacl/BrownZADWR24,
author = {Andrew Brown and
Jiading Zhu and
Mohamed Abdelwahab and
Alec Dong and
Cindy Wang and
Jonathan Rose},
editor = {Yvette Graham and
Matthew Purver},
title = {Generation, Distillation and Evaluation of Motivational Interviewing-Style
Reflections with a Foundational Language Model},
booktitle = {Proceedings of the 18th Conference of the European Chapter of the
Association for Computational Linguistics, {EACL} 2024 - Volume 1:
Long Papers, St. Julian's, Malta, March 17-22, 2024},
pages = {1241--1252},
publisher = {Association for Computational Linguistics},
year = {2024},
url = {https://aclanthology.org/2024.eacl-long.75},
timestamp = {Tue, 02 Apr 2024 16:32:10 +0200},
biburl = {https://dblp.org/rec/conf/eacl/BrownZADWR24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2402-01051,
author = {Andrew Brown and
Jiading Zhu and
Mohamed Abdelwahab and
Alec Dong and
Cindy Wang and
Jonathan Rose},
title = {Generation, Distillation and Evaluation of Motivational Interviewing-Style
Reflections with a Foundational Language Model},
journal = {CoRR},
volume = {abs/2402.01051},
year = {2024},
url = {https://doi.org/10.48550/arXiv.2402.01051},
doi = {10.48550/ARXIV.2402.01051},
eprinttype = {arXiv},
eprint = {2402.01051},
timestamp = {Fri, 09 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2402-01051.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sensors/BrousseauRE20,
author = {Braiden Brousseau and
Jonathan Rose and
Moshe Eizenman},
title = {Hybrid Eye-Tracking on a Smartphone with {CNN} Feature Extraction
and an Infrared 3D Model},
journal = {Sensors},
volume = {20},
number = {2},
pages = {543},
year = {2020},
url = {https://doi.org/10.3390/s20020543},
doi = {10.3390/S20020543},
timestamp = {Sat, 30 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sensors/BrousseauRE20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MurrayLWMWHYCKA20,
author = {Kevin E. Murray and
Jason Luu and
Matthew J. P. Walker and
Conor McCullough and
Sen Wang and
Safeen Huda and
Bo Yan and
Charles Chiasson and
Kenneth B. Kent and
Jason Helge Anderson and
Jonathan Rose and
Vaughn Betz},
title = {Optimizing {FPGA} Logic Block Architectures for Arithmetic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {28},
number = {6},
pages = {1378--1391},
year = {2020},
url = {https://doi.org/10.1109/TVLSI.2020.2965772},
doi = {10.1109/TVLSI.2020.2965772},
timestamp = {Thu, 06 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MurrayLWMWHYCKA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpr/ChughBRE20,
author = {Soumil Chugh and
Braiden Brousseau and
Jonathan Rose and
Moshe Eizenman},
title = {Detection and Correspondence Matching of Corneal Reflections for Eye
Tracking Using Deep Learning},
booktitle = {25th International Conference on Pattern Recognition, {ICPR} 2020,
Virtual Event / Milan, Italy, January 10-15, 2021},
pages = {2210--2217},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ICPR48806.2021.9412066},
doi = {10.1109/ICPR48806.2021.9412066},
timestamp = {Fri, 07 May 2021 08:42:33 +0200},
biburl = {https://dblp.org/rec/conf/icpr/ChughBRE20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WongBR18,
author = {Henry Wong and
Vaughn Betz and
Jonathan Rose},
title = {High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order
Soft Processors},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {1},
pages = {1:1--1:22},
year = {2018},
url = {https://doi.org/10.1145/3093741},
doi = {10.1145/3093741},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/WongBR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/RodionovR18,
author = {Alex Rodionov and
Jonathan Rose},
title = {Automatic Topology Optimization for {FPGA} Interconnect Synthesis},
booktitle = {28th International Conference on Field Programmable Logic and Applications,
{FPL} 2018, Dublin, Ireland, August 27-31, 2018},
pages = {30--34},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/FPL.2018.00013},
doi = {10.1109/FPL.2018.00013},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/RodionovR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/uemcom/BrousseauRE18,
author = {Braiden Brousseau and
Jonathan Rose and
Moshe Eizenman},
editor = {Satyajit Chakrabarti and
Himadri Nath Saha},
title = {SmartEye: An Accurate Infrared Eye Tracking System for Smartphones},
booktitle = {9th {IEEE} Annual Ubiquitous Computing, Electronics {\&} Mobile
Communication Conference, {UEMCON} 2018, New York City, NY, USA, November
8-10, 2018},
pages = {951--959},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/UEMCON.2018.8796799},
doi = {10.1109/UEMCON.2018.8796799},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/uemcom/BrousseauRE18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/africon/AndargieRAB17,
author = {Fitsum Assamnew Andargie and
Jonathan Rose and
Todd M. Austin and
Valeria Bertacco},
title = {Energy efficient object detection on the mobile {GP-GPU}},
booktitle = {{IEEE} {AFRICON} 2017, Cape Town, South Africa, September 18-20, 2017},
pages = {945--950},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/AFRCON.2017.8095609},
doi = {10.1109/AFRCON.2017.8095609},
timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
biburl = {https://dblp.org/rec/conf/africon/AndargieRAB17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/RodionovR17,
author = {Alex Rodionov and
Jonathan Rose},
editor = {Jonathan W. Greene and
Jason Helge Anderson},
title = {Synchronization Constraints for Interconnect Synthesis},
booktitle = {Proceedings of the 2017 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2017, Monterey, CA, USA, February 22-24, 2017},
pages = {95--104},
publisher = {{ACM}},
year = {2017},
url = {http://dl.acm.org/citation.cfm?id=3021729},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/RodionovR17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/RodionovBR16,
author = {Alex Rodionov and
David Biancolin and
Jonathan Rose},
title = {Fine-Grained Interconnect Synthesis},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {9},
number = {4},
pages = {31:1--31:22},
year = {2016},
url = {https://doi.org/10.1145/2892641},
doi = {10.1145/2892641},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/RodionovBR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WongBR16,
author = {Henry Wong and
Vaughn Betz and
Jonathan Rose},
title = {Microarchitecture and Circuits for a 200 MHz Out-of-Order Soft Processor
Memory System},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {10},
number = {1},
pages = {7:1--7:22},
year = {2016},
url = {https://doi.org/10.1145/2974022},
doi = {10.1145/2974022},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/WongBR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/WongBR16,
author = {Henry Wong and
Vaughn Betz and
Jonathan Rose},
title = {High Performance Instruction Scheduling Circuits for Out-of-Order
Soft Processors},
booktitle = {24th {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2016, Washington, DC, USA, May 1-3, 2016},
pages = {9--16},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/FCCM.2016.11},
doi = {10.1109/FCCM.2016.11},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/WongBR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/africon/AndargieR15,
author = {Fitsum Assamnew Andargie and
Jonathan Rose},
title = {Performance characterization of mobile GP-GPUs},
booktitle = {{AFRICON} 2015, Addis Ababa, Ethiopia, September 14-17, 2015},
pages = {1--6},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/AFRCON.2015.7332026},
doi = {10.1109/AFRCON.2015.7332026},
timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
biburl = {https://dblp.org/rec/conf/africon/AndargieR15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/RodionovBR15,
author = {Alex Rodionov and
David Biancolin and
Jonathan Rose},
editor = {George A. Constantinides and
Deming Chen},
title = {Fine-Grained Interconnect Synthesis},
booktitle = {Proceedings of the 2015 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, Monterey, CA, USA, February 22-24, 2015},
pages = {46--55},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2684746.2689061},
doi = {10.1145/2684746.2689061},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/RodionovBR15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/RodionovR15,
author = {Alex Rodionov and
Jonathan Rose},
title = {Automatic {FPGA} system and interconnect construction with multicast
and customizable topology},
booktitle = {2015 International Conference on Field Programmable Technology, {FPT}
2015, Queenstown, New Zealand, December 7-9, 2015},
pages = {72--79},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/FPT.2015.7393132},
doi = {10.1109/FPT.2015.7393132},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/RodionovR15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LuuGWSYNNWLAKARB14,
author = {Jason Luu and
Jeffrey Goeders and
Michael Wainberg and
Andrew Somerville and
Thien Yu and
Konstantin Nasartschuk and
Miad Nasr and
Sen Wang and
Tim Liu and
Nooruddin Ahmed and
Kenneth B. Kent and
Jason Helge Anderson and
Jonathan Rose and
Vaughn Betz},
title = {{VTR} 7.0: Next Generation Architecture and {CAD} System for FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {2},
pages = {6:1--6:30},
year = {2014},
url = {https://doi.org/10.1145/2617593},
doi = {10.1145/2617593},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LuuGWSYNNWLAKARB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WongBR14,
author = {Henry Wong and
Vaughn Betz and
Jonathan Rose},
title = {Quantifying the Gap Between {FPGA} and Custom {CMOS} to Aid Microarchitectural
Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {22},
number = {10},
pages = {2067--2080},
year = {2014},
url = {https://doi.org/10.1109/TVLSI.2013.2284281},
doi = {10.1109/TVLSI.2013.2284281},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WongBR14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/LuuMWHYCKARB14,
author = {Jason Luu and
Conor McCullough and
Sen Wang and
Safeen Huda and
Bo Yan and
Charles Chiasson and
Kenneth B. Kent and
Jason Helge Anderson and
Jonathan Rose and
Vaughn Betz},
title = {On Hard Adders and Carry Chains in FPGAs},
booktitle = {22nd {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2014, Boston, MA, USA, May 11-13, 2014},
pages = {52--59},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/FCCM.2014.25},
doi = {10.1109/FCCM.2014.25},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/LuuMWHYCKARB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LuuRA14,
author = {Jason Luu and
Jonathan Rose and
Jason Helge Anderson},
editor = {Vaughn Betz and
George A. Constantinides},
title = {Towards interconnect-adaptive packing for FPGAs},
booktitle = {The 2014 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} '14, Monterey, CA, {USA} - February 26 - 28, 2014},
pages = {21--30},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2554688.2554783},
doi = {10.1145/2554688.2554783},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LuuRA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/WongBR13,
author = {Henry Wong and
Vaughn Betz and
Jonathan Rose},
title = {Efficient methods for out-of-order load/store execution for high-performance
soft processors},
booktitle = {2013 International Conference on Field-Programmable Technology, {FPT}
2013, Kyoto, Japan, December 9-11, 2013},
pages = {442--445},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/FPT.2013.6718409},
doi = {10.1109/FPT.2013.6718409},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/WongBR13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ZhangBR12,
author = {Wei Zhang and
Vaughn Betz and
Jonathan Rose},
title = {Portable and scalable FPGA-based acceleration of a direct linear system
solver},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {5},
number = {1},
pages = {6:1--6:26},
year = {2012},
url = {https://doi.org/10.1145/2133352.2133358},
doi = {10.1145/2133352.2133358},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ZhangBR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YiannacourasSR12,
author = {Peter Yiannacouras and
J. Gregory Steffan and
Jonathan Rose},
title = {Portable, Flexible, and Scalable Soft Vector Processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {20},
number = {8},
pages = {1429--1442},
year = {2012},
url = {https://doi.org/10.1109/TVLSI.2011.2160463},
doi = {10.1109/TVLSI.2011.2160463},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YiannacourasSR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/RoseLYDGSKJA12,
author = {Jonathan Rose and
Jason Luu and
Chi Wai Yu and
Opal Densmore and
Jeffrey Goeders and
Andrew Somerville and
Kenneth B. Kent and
Peter Jamieson and
Jason Helge Anderson},
editor = {Katherine Compton and
Brad L. Hutchings},
title = {The {VTR} project: architecture and {CAD} for FPGAs from verilog to
routing},
booktitle = {Proceedings of the {ACM/SIGDA} 20th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2012, Monterey, California, USA,
February 22-24, 2012},
pages = {77--86},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2145694.2145708},
doi = {10.1145/2145694.2145708},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/RoseLYDGSKJA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/ShahR12,
author = {Niyati Shah and
Jonathan Rose},
editor = {Dirk Koch and
Satnam Singh and
Jim T{\o}rresen},
title = {On the difficulty of pin-to-wire routing in FPGAs},
booktitle = {22nd International Conference on Field Programmable Logic and Applications
(FPL), Oslo, Norway, August 29-31, 2012},
pages = {83--90},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/FPL.2012.6339245},
doi = {10.1109/FPL.2012.6339245},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/fpl/ShahR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/BrousseauR12,
author = {Braiden Brousseau and
Jonathan Rose},
title = {An energy-efficient, fast {FPGA} hardware architecture for OpenCV-Compatible
object detection},
booktitle = {2012 International Conference on Field-Programmable Technology, {FPT}
2012, Seoul, Korea (South), December 10-12, 2012},
pages = {166--173},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/FPT.2012.6412130},
doi = {10.1109/FPT.2012.6412130},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/BrousseauR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/almob/RodionovBRT11,
author = {Alex Rodionov and
Alexandr Bezginov and
Jonathan Rose and
Elisabeth R. M. Tillier},
title = {A new, fast algorithm for detecting protein coevolution using maximum
compatible cliques},
journal = {Algorithms Mol. Biol.},
volume = {6},
pages = {17},
year = {2011},
url = {https://doi.org/10.1186/1748-7188-6-17},
doi = {10.1186/1748-7188-6-17},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/almob/RodionovBRT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LuuKJCYFKR11,
author = {Jason Luu and
Ian Kuon and
Peter Jamieson and
Ted Campbell and
Andy Gean Ye and
Wei Mark Fang and
Kenneth B. Kent and
Jonathan Rose},
title = {{VPR} 5.0: {FPGA} {CAD} and architecture exploration tools with single-driver
routing, heterogeneity and process scaling},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {4},
pages = {32:1--32:23},
year = {2011},
url = {https://doi.org/10.1145/2068716.2068718},
doi = {10.1145/2068716.2068718},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LuuKJCYFKR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KuonR11,
author = {Ian Kuon and
Jonathan Rose},
title = {Exploring Area and Delay Tradeoffs in FPGAs With Architecture and
Automated Transistor Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {19},
number = {1},
pages = {71--84},
year = {2011},
url = {https://doi.org/10.1109/TVLSI.2009.2031318},
doi = {10.1109/TVLSI.2009.2031318},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KuonR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/RoseL11,
author = {Jonathan Rose and
Guy G. Lemieux},
editor = {John Wawrzynek and
Katherine Compton},
title = {The role of FPGAs in a converged future with heterogeneous programmable
processors: pre-conference workshop},
booktitle = {Proceedings of the {ACM/SIGDA} 19th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2011, Monterey, California, USA,
February 27, March 1, 2011},
pages = {1--2},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1950413.1950415},
doi = {10.1145/1950413.1950415},
timestamp = {Tue, 06 Nov 2018 16:58:23 +0100},
biburl = {https://dblp.org/rec/conf/fpga/RoseL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/WongBR11,
author = {Henry Wong and
Vaughn Betz and
Jonathan Rose},
editor = {John Wawrzynek and
Katherine Compton},
title = {Comparing {FPGA} vs. custom cmos and the impact on processor microarchitecture},
booktitle = {Proceedings of the {ACM/SIGDA} 19th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2011, Monterey, California, USA,
February 27, March 1, 2011},
pages = {5--14},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1950413.1950419},
doi = {10.1145/1950413.1950419},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/WongBR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LuuAR11,
author = {Jason Luu and
Jason Helge Anderson and
Jonathan Rose},
editor = {John Wawrzynek and
Katherine Compton},
title = {Architecture description and packing for logic blocks with hierarchy,
modes and complex interconnect},
booktitle = {Proceedings of the {ACM/SIGDA} 19th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2011, Monterey, California, USA,
February 27, March 1, 2011},
pages = {227--236},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1950413.1950457},
doi = {10.1145/1950413.1950457},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LuuAR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JamiesonR10,
author = {Peter A. Jamieson and
Jonathan Rose},
title = {Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow
Clusters},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {18},
number = {12},
pages = {1696--1709},
year = {2010},
url = {https://doi.org/10.1109/TVLSI.2009.2026651},
doi = {10.1109/TVLSI.2009.2026651},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JamiesonR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/bcb/RodionovBRT10,
author = {Alex Rodionov and
Alexandr Bezginov and
Jonathan Rose and
Elisabeth R. M. Tillier},
editor = {Aidong Zhang and
Mark Borodovsky and
Gultekin {\"{O}}zsoyoglu and
Armin R. Mikler},
title = {Faster coevolution detection of proteins using maximum similar cliques},
booktitle = {Proceedings of the First {ACM} International Conference on Bioinformatics
and Computational Biology, {BCB} 2010, Niagara Falls, NY, USA, August
2-4, 2010},
pages = {484--486},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1854776.1854865},
doi = {10.1145/1854776.1854865},
timestamp = {Tue, 01 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/bcb/RodionovBRT10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/YiannacourasSR09,
author = {Peter Yiannacouras and
J. Gregory Steffan and
Jonathan Rose},
editor = {J{\"{o}}rg Henkel and
Sri Parameswaran},
title = {Fine-grain performance scaling of soft vector processors},
booktitle = {Proceedings of the 2009 International Conference on Compilers, Architecture,
and Synthesis for Embedded Systems, {CASES} 2009, Grenoble, France,
October 11-16, 2009},
pages = {97--106},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1629395.1629411},
doi = {10.1145/1629395.1629411},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/YiannacourasSR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/LuuRLCLR09,
author = {Jason Luu and
Keith Redmond and
William Lo and
Paul Chow and
Lothar Lilge and
Jonathan Rose},
editor = {Kenneth L. Pocek and
Duncan A. Buell},
title = {FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic
Cancer Therapy},
booktitle = {{FCCM} 2009, 17th {IEEE} Symposium on Field Programmable Custom Computing
Machines, Napa, California, USA, 5-7 April 2009, Proceedings},
pages = {157--164},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/FCCM.2009.24},
doi = {10.1109/FCCM.2009.24},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/LuuRLCLR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LuuKJCYFR09,
author = {Jason Luu and
Ian Kuon and
Peter Jamieson and
Ted Campbell and
Andy Gean Ye and
Wei Mark Fang and
Jonathan Rose},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {{VPR} 5.0: {FPGA} cad and architecture exploration tools with single-driver
routing, heterogeneity and process scaling},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {133--142},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508150},
doi = {10.1145/1508128.1508150},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/LuuKJCYFR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/YiannacourasSR09,
author = {Peter Yiannacouras and
J. Gregory Steffan and
Jonathan Rose},
editor = {Paul Chow and
Peter Y. K. Cheung},
title = {Soft vector processors vs {FPGA} custom hardware: measuring and reducing
the gap},
booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA,
February 22-24, 2009},
pages = {277},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1508128.1508178},
doi = {10.1145/1508128.1508178},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/YiannacourasSR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/Rose09,
author = {Jonathan Rose},
editor = {Martin Danek and
Jiri Kadlec and
Brent E. Nelson},
title = {The evolution of architecture exploration of programmable devices},
booktitle = {19th International Conference on Field Programmable Logic and Applications,
{FPL} 2009, August 31 - September 2, 2009, Prague, Czech Republic},
pages = {3},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/FPL.2009.5272566},
doi = {10.1109/FPL.2009.5272566},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/fpl/Rose09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/YiannacourasSR09,
author = {Peter Yiannacouras and
J. Gregory Steffan and
Jonathan Rose},
editor = {Martin Danek and
Jiri Kadlec and
Brent E. Nelson},
title = {Data parallel {FPGA} workloads: Software versus hardware},
booktitle = {19th International Conference on Field Programmable Logic and Applications,
{FPL} 2009, August 31 - September 2, 2009, Prague, Czech Republic},
pages = {51--58},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/FPL.2009.5272551},
doi = {10.1109/FPL.2009.5272551},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/YiannacourasSR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/YiannacourasSR08,
author = {Peter Yiannacouras and
J. Gregory Steffan and
Jonathan Rose},
editor = {Erik R. Altman},
title = {{VESPA:} portable, scalable, and flexible FPGA-based vector processors},
booktitle = {Proceedings of the 2008 International Conference on Compilers, Architecture,
and Synthesis for Embedded Systems, {CASES} 2008, Atlanta, GA, USA,
October 19-24, 2008},
pages = {61--70},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1450095.1450107},
doi = {10.1145/1450095.1450107},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/YiannacourasSR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KuonR08,
author = {Ian Kuon and
Jonathan Rose},
editor = {Limor Fix},
title = {Automated transistor sizing for {FPGA} architecture exploration},
booktitle = {Proceedings of the 45th Design Automation Conference, {DAC} 2008,
Anaheim, CA, USA, June 8-13, 2008},
pages = {792--795},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1391469.1391671},
doi = {10.1145/1391469.1391671},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/KuonR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/FangR08,
author = {Wei Mark Fang and
Jonathan Rose},
editor = {Mike Hutton and
Paul Chow},
title = {Modeling routing demand for early-stage {FPGA} architecture development},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {139--148},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344694},
doi = {10.1145/1344671.1344694},
timestamp = {Tue, 06 Nov 2018 16:58:23 +0100},
biburl = {https://dblp.org/rec/conf/fpga/FangR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/KuonR08,
author = {Ian Kuon and
Jonathan Rose},
editor = {Mike Hutton and
Paul Chow},
title = {Area and delay trade-offs in the circuit and architecture design of
FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA,
February 24-26, 2008},
pages = {149--158},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1344671.1344695},
doi = {10.1145/1344671.1344695},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/KuonR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/ZhangBR08,
author = {Wei Zhang and
Vaughn Betz and
Jonathan Rose},
editor = {Tarek A. El{-}Ghazawi and
Yao{-}Wen Chang and
Juinn{-}Dar Huang and
Proshanta Saha},
title = {Portable and scalable FPGA-based acceleration of a direct linear system
solver},
booktitle = {2008 International Conference on Field-Programmable Technology, {FPT}
2008, Taipei, Taiwan, December 7-10, 2008},
pages = {17--24},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/FPT.2008.4762361},
doi = {10.1109/FPT.2008.4762361},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/ZhangBR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/fteda/KuonTR07,
author = {Ian Kuon and
Russell Tessier and
Jonathan Rose},
title = {{FPGA} Architecture: Survey and Challenges},
journal = {Found. Trends Electron. Des. Autom.},
volume = {2},
number = {2},
pages = {135--253},
year = {2007},
url = {https://doi.org/10.1561/1000000005},
doi = {10.1561/1000000005},
timestamp = {Thu, 18 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/fteda/KuonTR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KuonR07,
author = {Ian Kuon and
Jonathan Rose},
title = {Measuring the Gap Between FPGAs and ASICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {2},
pages = {203--215},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.884574},
doi = {10.1109/TCAD.2006.884574},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KuonR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YiannacourasSR07,
author = {Peter Yiannacouras and
J. Gregory Steffan and
Jonathan Rose},
title = {Exploration and Customization of FPGA-Based Soft Processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {26},
number = {2},
pages = {266--277},
year = {2007},
url = {https://doi.org/10.1109/TCAD.2006.887921},
doi = {10.1109/TCAD.2006.887921},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YiannacourasSR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/JamiesonR07,
author = {Peter Jamieson and
Jonathan Rose},
editor = {Hideharu Amano and
Andy Ye and
Takeshi Ikenaga},
title = {Architecting Hard Crossbars on FPGAs and Increasing their Area Efficiency
with Shadow Clusters},
booktitle = {2007 International Conference on Field-Programmable Technology, {ICFPT}
2007, Kitakyushu, Japan, December 12-14, 2007},
pages = {57--64},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/FPT.2007.4439232},
doi = {10.1109/FPT.2007.4439232},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/JamiesonR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mva/DarabihaMR06,
author = {Ahmad Darabiha and
W. James MacLean and
Jonathan Rose},
title = {Reconfigurable hardware implementation of a phase-correlation stereoalgorithm},
journal = {Mach. Vis. Appl.},
volume = {17},
number = {2},
pages = {116--132},
year = {2006},
url = {https://doi.org/10.1007/s00138-006-0018-2},
doi = {10.1007/S00138-006-0018-2},
timestamp = {Wed, 17 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mva/DarabihaMR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YeR06,
author = {Andy Gean Ye and
Jonathan Rose},
title = {Using Bus-Based Connections to Improve Field-Programmable Gate-Array
Density for Implementing Datapath Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {14},
number = {5},
pages = {462--473},
year = {2006},
url = {https://doi.org/10.1109/TVLSI.2006.876095},
doi = {10.1109/TVLSI.2006.876095},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YeR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/KuonR06,
author = {Ian Kuon and
Jonathan Rose},
editor = {Steven J. E. Wilton and
Andr{\'{e}} DeHon},
title = {Measuring the gap between FPGAs and ASICs},
booktitle = {Proceedings of the {ACM/SIGDA} 14th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2006, Monterey, California, USA,
February 22-24, 2006},
pages = {21--30},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1117201.1117205},
doi = {10.1145/1117201.1117205},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/KuonR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/YiannacourasSR06,
author = {Peter Yiannacouras and
J. Gregory Steffan and
Jonathan Rose},
editor = {Steven J. E. Wilton and
Andr{\'{e}} DeHon},
title = {Application-specific customization of soft processor microarchitecture},
booktitle = {Proceedings of the {ACM/SIGDA} 14th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2006, Monterey, California, USA,
February 22-24, 2006},
pages = {201--210},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1117201.1117231},
doi = {10.1145/1117201.1117231},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/YiannacourasSR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/JamiesonR06,
author = {Peter Jamieson and
Jonathan Rose},
editor = {George A. Constantinides and
Wai{-}Kei Mak and
Phaophak Sirisuk and
Theerayod Wiangtong},
title = {Enhancing the area-efficiency of FPGAs with hard circuits using shadow
clusters},
booktitle = {2006 {IEEE} International Conference on Field Programmable Technology,
{FPT} 2006, Bangkok, Thailand, December 13-15, 2006},
pages = {1--8},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/FPT.2006.270384},
doi = {10.1109/FPT.2006.270384},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/JamiesonR06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/Rose06,
author = {Jonathan Rose},
editor = {George A. Constantinides and
Wai{-}Kei Mak and
Phaophak Sirisuk and
Theerayod Wiangtong},
title = {Invited Keynote 1: Closing the gap between FPGAs and ASICs},
booktitle = {2006 {IEEE} International Conference on Field Programmable Technology,
{FPT} 2006, Bangkok, Thailand, December 13-15, 2006},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/FPT.2006.270375},
doi = {10.1109/FPT.2006.270375},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/Rose06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/YiannacourasRS05,
author = {Peter Yiannacouras and
Jonathan Rose and
J. Gregory Steffan},
editor = {Thomas M. Conte and
Paolo Faraboschi and
William H. Mangione{-}Smith and
Walid A. Najjar},
title = {The microarchitecture of FPGA-based soft processors},
booktitle = {Proceedings of the 2005 International Conference on Compilers, Architecture,
and Synthesis for Embedded Systems, {CASES} 2005, San Francisco, California,
USA, September 24-27, 2005},
pages = {202--212},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1086297.1086325},
doi = {10.1145/1086297.1086325},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/YiannacourasRS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/YeR05,
author = {Andy Gean Ye and
Jonathan Rose},
editor = {Herman Schmit and
Steven J. E. Wilton},
title = {Using bus-based connections to improve field-programmable gate array
density for implementing datapath circuits},
booktitle = {Proceedings of the {ACM/SIGDA} 13th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2005, Monterey, California, USA,
February 20-22, 2005},
pages = {3--13},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1046192.1046194},
doi = {10.1145/1046192.1046194},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/YeR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LewisABBBCGHLLLMMPPPRRSSYCR05,
author = {David M. Lewis and
Elias Ahmed and
Gregg Baeckler and
Vaughn Betz and
Mark Bourgeault and
David Cashman and
David R. Galloway and
Mike Hutton and
Christopher Lane and
Andy Lee and
Paul Leventis and
Sandy Marquardt and
Cameron McClintock and
Ketan Padalia and
Bruce Pedersen and
Giles Powell and
Boris Ratchev and
Srinivas Reddy and
Jay Schleicher and
Kevin Stevens and
Richard Yuan and
Richard Cliff and
Jonathan Rose},
editor = {Herman Schmit and
Steven J. E. Wilton},
title = {The Stratix {II} logic and routing architecture},
booktitle = {Proceedings of the {ACM/SIGDA} 13th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2005, Monterey, California, USA,
February 20-22, 2005},
pages = {14--20},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1046192.1046195},
doi = {10.1145/1046192.1046195},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LewisABBBCGHLLLMMPPPRRSSYCR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/KuonER05,
author = {Ian Kuon and
Aaron Egier and
Jonathan Rose},
editor = {Herman Schmit and
Steven J. E. Wilton},
title = {Design, layout and verification of an {FPGA} using automated tools},
booktitle = {Proceedings of the {ACM/SIGDA} 13th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2005, Monterey, California, USA,
February 20-22, 2005},
pages = {215--226},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1046192.1046220},
doi = {10.1145/1046192.1046220},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/KuonER05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/YeR05,
author = {Andy Gean Ye and
Jonathan Rose},
editor = {Tero Rissa and
Steven J. E. Wilton and
Philip Heng Wai Leong},
title = {Measuring and Utilizing the Correlation Between Signal Connectivity
and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks},
booktitle = {Proceedings of the 2005 International Conference on Field Programmable
Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005},
pages = {159--166},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/FPL.2005.1515716},
doi = {10.1109/FPL.2005.1515716},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/YeR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/JamiesonR05,
author = {Peter Jamieson and
Jonathan Rose},
editor = {Tero Rissa and
Steven J. E. Wilton and
Philip Heng Wai Leong},
title = {A Verilog {RTL} Synthesis Tool for Heterogeneous FPGAs},
booktitle = {Proceedings of the 2005 International Conference on Field Programmable
Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005},
pages = {305--310},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/FPL.2005.1515739},
doi = {10.1109/FPL.2005.1515739},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/JamiesonR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/FenderRG05,
author = {Joshua Fender and
Jonathan Rose and
David R. Galloway},
editor = {Gordon J. Brebner and
Samarjit Chakraborty and
Weng{-}Fai Wong},
title = {The Transmogrifier-4: An FPGA-Based Hardware Development System with
Multi-Gigabyte Memory Capacity and High Host and Memory Bandwidth},
booktitle = {Proceedings of the 2005 {IEEE} International Conference on Field-Programmable
Technology, {FPT} 2005, 11-14 December 2005, Singapore},
pages = {301--302},
publisher = {{IEEE}},
year = {2005},
timestamp = {Tue, 19 Jun 2018 20:15:46 +0200},
biburl = {https://dblp.org/rec/conf/fpt/FenderRG05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KundarewichR04,
author = {Paul D. Kundarewich and
Jonathan Rose},
title = {Synthetic circuit generation using clustering and iteration},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {23},
number = {6},
pages = {869--887},
year = {2004},
url = {https://doi.org/10.1109/TCAD.2004.828132},
doi = {10.1109/TCAD.2004.828132},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KundarewichR04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AhmedR04,
author = {Elias Ahmed and
Jonathan Rose},
title = {The effect of {LUT} and cluster size on deep-submicron {FPGA} performance
and density},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {12},
number = {3},
pages = {288--298},
year = {2004},
url = {https://doi.org/10.1109/TVLSI.2004.824300},
doi = {10.1109/TVLSI.2004.824300},
timestamp = {Fri, 10 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/AhmedR04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/CzajkowskiR04,
author = {Tomasz S. Czajkowski and
Jonathan Rose},
editor = {Russell Tessier and
Herman Schmit},
title = {A synthesis oriented omniscient manual editor},
booktitle = {Proceedings of the {ACM/SIGDA} 12th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2004, Monterey, California, USA,
February 22-24, 2004},
pages = {89--98},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/968280.968295},
doi = {10.1145/968280.968295},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/CzajkowskiR04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/KuonER04,
author = {Ian Kuon and
Aaron Egier and
Jonathan Rose},
editor = {Russell Tessier and
Herman Schmit},
title = {Transistor grouping and metal layer trade-offs in automatic tile layout
of FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} 12th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2004, Monterey, California, USA,
February 22-24, 2004},
pages = {249},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/968280.968327},
doi = {10.1145/968280.968327},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/KuonER04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/AlexRIH04,
author = {Anish Alex and
Jonathan Rose and
Ruth Isserlin{-}Weinberger and
Christopher W. V. Hogue},
editor = {J{\"{u}}rgen Becker and
Marco Platzner and
Serge Vernalde},
title = {Hardware Accelerated Novel Protein Identification},
booktitle = {Field Programmable Logic and Application, 14th International Conference
, {FPL} 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3203},
pages = {13--22},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30117-2\_4},
doi = {10.1007/978-3-540-30117-2\_4},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/AlexRIH04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/YeR04,
author = {Andy Gean Ye and
Jonathan Rose},
editor = {Oliver Diessel and
John Williams},
title = {Using multi-bit logic blocks and automated packing to improve field-programmable
gate array density for implementing datapath circuits},
booktitle = {Proceedings of the 2004 {IEEE} International Conference on Field-Programmable
Technology, Brisbane, Australia, December 6-8, 2004},
pages = {129--136},
publisher = {{IEEE}},
year = {2004},
url = {https://doi.org/10.1109/FPT.2004.1393260},
doi = {10.1109/FPT.2004.1393260},
timestamp = {Fri, 22 Nov 2019 15:44:53 +0100},
biburl = {https://dblp.org/rec/conf/fpt/YeR04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/Rose04,
author = {Jonathan Rose},
title = {Hard vs. Soft: The Central Question of Pre-Fabricated Silicon},
booktitle = {34th {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2004), 19-22 May 2004, Toronto, Canada},
pages = {2--5},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ISMVL.2004.1319911},
doi = {10.1109/ISMVL.2004.1319911},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/Rose04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/YeRL03,
author = {Andy Gean Ye and
Jonathan Rose and
David M. Lewis},
title = {Architecture of datapath-oriented coarse-grain logic and routing for
FPGAs},
booktitle = {Proceedings of the {IEEE} Custom Integrated Circuits Conference, {CICC}
2003, San Jose, CA, USA, September 21 - 24, 2003},
pages = {61--64},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/CICC.2003.1249360},
doi = {10.1109/CICC.2003.1249360},
timestamp = {Wed, 08 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cicc/YeRL03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cvpr/DarabihaRM03,
author = {Ahmad Darabiha and
Jonathan Rose and
W. James MacLean},
title = {Video-Rate Stereo Depth Measurement on Programmable Hardware},
booktitle = {2003 {IEEE} Computer Society Conference on Computer Vision and Pattern
Recognition {(CVPR} 2003), 16-22 June 2003, Madison, WI, {USA}},
pages = {203--210},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/CVPR.2003.1211355},
doi = {10.1109/CVPR.2003.1211355},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cvpr/DarabihaRM03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LewisBJLLLMMPPRWCR03,
author = {David M. Lewis and
Vaughn Betz and
David Jefferson and
Andy Lee and
Christopher Lane and
Paul Leventis and
Sandy Marquardt and
Cameron McClintock and
Bruce Pedersen and
Giles Powell and
Srinivas Reddy and
Chris Wysocki and
Richard Cliff and
Jonathan Rose},
editor = {Steve Trimberger and
Russell Tessier},
title = {The Stratix\({}^{\mbox{TM}}\) routing and logic architecture},
booktitle = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
Gate Arrays, {FPGA} 2003, Monterey, CA, USA, February 23-25, 2003},
pages = {12--20},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/611817.611821},
doi = {10.1145/611817.611821},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LewisBJLLLMMPPRWCR03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/PadaliaFBER03,
author = {Ketan Padalia and
Ryan Fung and
Mark Bourgeault and
Aaron Egier and
Jonathan Rose},
editor = {Steve Trimberger and
Russell Tessier},
title = {Automatic transistor and physical design of {FPGA} tiles from an architectural
specification},
booktitle = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
Gate Arrays, {FPGA} 2003, Monterey, CA, USA, February 23-25, 2003},
pages = {164--172},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/611817.611842},
doi = {10.1145/611817.611842},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/PadaliaFBER03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/KundarewichR03,
author = {Paul D. Kundarewich and
Jonathan Rose},
editor = {Steve Trimberger and
Russell Tessier},
title = {Synthetic circuit generation using clustering and iteration},
booktitle = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
Gate Arrays, {FPGA} 2003, Monterey, CA, USA, February 23-25, 2003},
pages = {245},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/611817.611875},
doi = {10.1145/611817.611875},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/KundarewichR03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/FenderR03,
author = {Joshua Fender and
Jonathan Rose},
title = {A high-speed ray tracing engine built on a field-programmable system},
booktitle = {Proceedings of the 2003 {IEEE} International Conference on Field-Programmable
Technology, Tokyo, Japan, {FPT} 2003, December 15-17, 2003},
pages = {188--195},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/FPT.2003.1275747},
doi = {10.1109/FPT.2003.1275747},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/FenderR03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/YiannacourasR03,
author = {Peter Yiannacouras and
Jonathan Rose},
title = {A parameterized automatic cache generator for FPGAs},
booktitle = {Proceedings of the 2003 {IEEE} International Conference on Field-Programmable
Technology, Tokyo, Japan, {FPT} 2003, December 15-17, 2003},
pages = {324--327},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/FPT.2003.1275768},
doi = {10.1109/FPT.2003.1275768},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/YiannacourasR03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuttonRC02,
author = {Michael D. Hutton and
Jonathan Rose and
Derek G. Corneil},
title = {Automatic generation of synthetic sequential benchmark circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {8},
pages = {928--940},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.800456},
doi = {10.1109/TCAD.2002.800456},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuttonRC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/RoopchansinghR02,
author = {Ajay Roopchansingh and
Jonathan Rose},
title = {Nearest neighbour interconnect architecture in deep submicron FPGAs},
booktitle = {Proceedings of the {IEEE} 2002 Custom Integrated Circuits Conference,
{CICC} 2002, Orlando, FL, USA, May 12-15, 2002},
pages = {59--62},
publisher = {{IEEE}},
year = {2002},
url = {https://doi.org/10.1109/CICC.2002.1012766},
doi = {10.1109/CICC.2002.1012766},
timestamp = {Tue, 04 Oct 2022 22:39:17 +0200},
biburl = {https://dblp.org/rec/conf/cicc/RoopchansinghR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ChowR02,
author = {William Chow and
Jonathan Rose},
editor = {Martine D. F. Schlag and
Steve Trimberger},
title = {{EVE:} a {CAD} tool for manual placement and pipelining assistance
of {FPGA} circuits},
booktitle = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
Gate Arrays, {FPGA} 2002, Monterey, CA, USA, February 24-26, 2002},
pages = {85--94},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/503048.503061},
doi = {10.1145/503048.503061},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ChowR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/YeRL02,
author = {Andy Gean Ye and
Jonathan Rose and
David M. Lewis},
title = {Synthesizing datapath circuits for FPGAs with emphasis on area minimization},
booktitle = {Proceedings of the 2002 {IEEE} International Conference on Field-Programmable
Technology, {FPT} 2002, Hong Kong, China, December 16-18, 2002},
pages = {219--226},
publisher = {{IEEE}},
year = {2002},
url = {https://doi.org/10.1109/FPT.2002.1188685},
doi = {10.1109/FPT.2002.1188685},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/YeRL02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WiltonRV01,
author = {Steven J. E. Wilton and
Jonathan Rose and
Zvonko G. Vranesic},
title = {Structural analysis and generation of synthetic digital circuits with
memory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {9},
number = {1},
pages = {223--226},
year = {2001},
url = {https://doi.org/10.1109/92.920838},
doi = {10.1109/92.920838},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WiltonRV01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/RutenbarBDJORS01,
author = {Rob A. Rutenbar and
Max Baron and
Thomas Daniel and
Rajeev Jayaraman and
Zvi Or{-}Bach and
Jonathan Rose and
Carl Sechen},
title = {Panel: (When) Will FPGAs Kill ASICs?},
booktitle = {Proceedings of the 38th Design Automation Conference, {DAC} 2001,
Las Vegas, NV, USA, June 18-22, 2001},
pages = {321--322},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/378239.378499},
doi = {10.1145/378239.378499},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/RutenbarBDJORS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ShengR01,
author = {Mike Sheng and
Jonathan Rose},
editor = {Scott Hauck and
Martine D. F. Schlag and
Russell Tessier},
title = {Mixing buffers and pass transistors in {FPGA} routing architectures},
booktitle = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
pages = {75--84},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/360276.360302},
doi = {10.1145/360276.360302},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ShengR01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KhalidR00,
author = {Mohammed A. S. Khalid and
Jonathan Rose},
title = {A novel and efficient routing architecture for multi-FPGA systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {8},
number = {1},
pages = {30--39},
year = {2000},
url = {https://doi.org/10.1109/92.820759},
doi = {10.1109/92.820759},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KhalidR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MarquardtBR00,
author = {Alexander Marquardt and
Vaughn Betz and
Jonathan Rose},
title = {Speed and area tradeoffs in cluster-based {FPGA} architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {8},
number = {1},
pages = {84--93},
year = {2000},
url = {https://doi.org/10.1109/92.820764},
doi = {10.1109/92.820764},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MarquardtBR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/AhmedR00,
author = {Elias Ahmed and
Jonathan Rose},
editor = {Steve Trimberger and
Scott Hauck},
title = {The effect of {LUT} and cluster size on deep-submicron {FPGA} performance
and density},
booktitle = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
Gate Arrays, {FPGA} 2000, Monterey, CA, USA, February 10-11, 2000},
pages = {3--12},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/329166.329171},
doi = {10.1145/329166.329171},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/AhmedR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/BetzR00,
author = {Vaughn Betz and
Jonathan Rose},
editor = {Steve Trimberger and
Scott Hauck},
title = {Automatic generation of {FPGA} routing architectures from high-level
descriptions},
booktitle = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
Gate Arrays, {FPGA} 2000, Monterey, CA, USA, February 10-11, 2000},
pages = {175--184},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/329166.329203},
doi = {10.1145/329166.329203},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/BetzR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/MarquardtBR00,
author = {Alexander Marquardt and
Vaughn Betz and
Jonathan Rose},
editor = {Steve Trimberger and
Scott Hauck},
title = {Timing-driven placement for FPGAs},
booktitle = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
Gate Arrays, {FPGA} 2000, Monterey, CA, USA, February 10-11, 2000},
pages = {203--213},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/329166.329208},
doi = {10.1145/329166.329208},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/MarquardtBR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/McCreadyR00,
author = {Rob McCready and
Jonathan Rose},
editor = {Steve Trimberger and
Scott Hauck},
title = {Real-time, frame-rate face detection on a configurable hardware system
(poster abstract)},
booktitle = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
Gate Arrays, {FPGA} 2000, Monterey, CA, USA, February 10-11, 2000},
pages = {221},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/329166.329221},
doi = {10.1145/329166.329221},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/McCreadyR00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@book{DBLP:books/kl/BetzRM99,
author = {Vaughn Betz and
Jonathan Rose and
Alexander Marquardt},
title = {Architecture and {CAD} for Deep-Submicron {FPGAS}},
series = {The Springer International Series in Engineering and Computer Science},
volume = {497},
publisher = {Kluwer},
year = {1999},
url = {https://doi.org/10.1007/978-1-4615-5145-4},
doi = {10.1007/978-1-4615-5145-4},
isbn = {978-1-4613-7342-1},
timestamp = {Tue, 23 Jul 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/books/kl/BetzRM99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WiltonRV99,
author = {Steven J. E. Wilton and
Jonathan Rose and
Zvonko G. Vranesic},
title = {The memory/logic interface in FPGAs with large embedded memory arrays},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {7},
number = {1},
pages = {80--91},
year = {1999},
url = {https://doi.org/10.1109/92.748203},
doi = {10.1109/92.748203},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WiltonRV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChowSRCPR99,
author = {Paul Chow and
Soon Ong Seo and
Jonathan Rose and
Kevin Chung and
Gerard P{\'{a}}ez{-}Monz{\'{o}}n and
Immanuel Rahardja},
title = {The design of an SRAM-based field-programmable gate array. I. Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {7},
number = {2},
pages = {191--197},
year = {1999},
url = {https://doi.org/10.1109/92.766746},
doi = {10.1109/92.766746},
timestamp = {Mon, 11 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChowSRCPR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChowSRCPR99a,
author = {Paul Chow and
Soon Ong Seo and
Jonathan Rose and
Kevin Chung and
Gerard P{\'{a}}ez{-}Monz{\'{o}}n and
Immanuel Rahardja},
title = {The design of a SRAM-based field-programmable gate array-Part {II:}
Circuit design and layout},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {7},
number = {3},
pages = {321--330},
year = {1999},
url = {https://doi.org/10.1109/92.784093},
doi = {10.1109/92.784093},
timestamp = {Wed, 14 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChowSRCPR99a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/MarquardtBR99,
author = {Alexander Marquardt and
Vaughn Betz and
Jonathan Rose},
editor = {Sinan Kaptanoglu and
Steve Trimberger},
title = {Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve
{FPGA} Speed and Density},
booktitle = {Proceedings of the 1999 {ACM/SIGDA} Seventh International Symposium
on Field Programmable Gate Arrays, {FPGA} 1999, Monterey, CA, USA,
February 21-23, 1999},
pages = {37--46},
publisher = {{ACM}},
year = {1999},
url = {https://doi.org/10.1145/296399.296426},
doi = {10.1145/296399.296426},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/MarquardtBR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/BetzR99,
author = {Vaughn Betz and
Jonathan Rose},
editor = {Sinan Kaptanoglu and
Steve Trimberger},
title = {{FPGA} Routing Architecture: Segmentation and Buffering to Optimize
Speed and Density},
booktitle = {Proceedings of the 1999 {ACM/SIGDA} Seventh International Symposium
on Field Programmable Gate Arrays, {FPGA} 1999, Monterey, CA, USA,
February 21-23, 1999},
pages = {59--68},
publisher = {{ACM}},
year = {1999},
url = {https://doi.org/10.1145/296399.296428},
doi = {10.1145/296399.296428},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/BetzR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/SankarR99,
author = {Yaska Sankar and
Jonathan Rose},
editor = {Sinan Kaptanoglu and
Steve Trimberger},
title = {Trading Quality for Compile Time: Ultra-Fast Placement for FPGAs},
booktitle = {Proceedings of the 1999 {ACM/SIGDA} Seventh International Symposium
on Field Programmable Gate Arrays, {FPGA} 1999, Monterey, CA, USA,
February 21-23, 1999},
pages = {157--166},
publisher = {{ACM}},
year = {1999},
url = {https://doi.org/10.1145/296399.296449},
doi = {10.1145/296399.296449},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/SankarR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/KhalidR99,
author = {Mohammed A. S. Khalid and
Jonathan Rose},
editor = {Jos{\'{e}} D. P. Rolim and
Frank Mueller and
Albert Y. Zomaya and
Fikret Er{\c{c}}al and
Stephan Olariu and
Binoy Ravindran and
Jan Gustafsson and
Hiroaki Takada and
Ronald A. Olsson and
Laxmikant V. Kal{\'{e}} and
Peter H. Beckman and
Matthew Haines and
Hossam A. ElGindy and
Denis Caromel and
Serge Chaumette and
Geoffrey C. Fox and
Yi Pan and
Keqin Li and
Tao Yang and
G. Ghiola and
Gianni Conte and
Luigi V. Mancini and
Dominique M{\'{e}}ry and
Beverly A. Sanders and
Devesh Bhatt and
Viktor K. Prasanna},
title = {Hardwired-Clusters Partial-Crossbar: {A} Hierarchical Routing Architecture
for Multi-FPGA Systems},
booktitle = {Parallel and Distributed Processing, 11 IPPS/SPDP'99 Workshops Held
in Conjunction with the 13th International Parallel Processing Symposium
and 10th Symposium on Parallel and Distributed Processing, San Juan,
Puerto Rico, USA, April 12-16, 1999, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1586},
pages = {597--605},
publisher = {Springer},
year = {1999},
url = {https://doi.org/10.1007/BFb0097944},
doi = {10.1007/BFB0097944},
timestamp = {Mon, 22 Mar 2021 14:03:05 +0100},
biburl = {https://dblp.org/rec/conf/ipps/KhalidR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/HuttonR99,
author = {Michael D. Hutton and
Jonathan Rose},
title = {Equivalence classes of clone circuits for physical-design benchmarking},
booktitle = {Proceedings of the 1999 International Symposium on Circuits and Systems,
{ISCAS} 1999, Orlando, Florida, USA, May 30 - June 2, 1999},
pages = {428--431},
publisher = {{IEEE}},
year = {1999},
url = {https://doi.org/10.1109/ISCAS.1999.780186},
doi = {10.1109/ISCAS.1999.780186},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/HuttonR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/HuttonR99a,
author = {Michael D. Hutton and
Jonathan Rose},
title = {Applications of clone circuits to issues in physical-design},
booktitle = {Proceedings of the 1999 International Symposium on Circuits and Systems,
{ISCAS} 1999, Orlando, Florida, USA, May 30 - June 2, 1999},
pages = {448--451},
publisher = {{IEEE}},
year = {1999},
url = {https://doi.org/10.1109/ISCAS.1999.780191},
doi = {10.1109/ISCAS.1999.780191},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/HuttonR99a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/BetzR98,
author = {Vaughn Betz and
Jonathan Rose},
title = {How Much Logic Should Go in an {FPGA} Logic Block?},
journal = {{IEEE} Des. Test Comput.},
volume = {15},
number = {1},
pages = {10--15},
year = {1998},
url = {https://doi.org/10.1109/54.655177},
doi = {10.1109/54.655177},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/BetzR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuttonRGC98,
author = {Michael D. Hutton and
Jonathan Rose and
Jerry P. Grossman and
Derek G. Corneil},
title = {Characterization and parameterized generation of synthetic combinational
benchmark circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {17},
number = {10},
pages = {985--996},
year = {1998},
url = {https://doi.org/10.1109/43.728919},
doi = {10.1109/43.728919},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuttonRGC98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LewisGIRC98,
author = {David M. Lewis and
David R. Galloway and
Marcus van Ierssel and
Jonathan Rose and
Paul Chow},
title = {The Transmogrifier-2: a 1 million gate rapid-prototyping system},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {6},
number = {2},
pages = {188--198},
year = {1998},
url = {https://doi.org/10.1109/92.678867},
doi = {10.1109/92.678867},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LewisGIRC98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BetzR98,
author = {Vaughn Betz and
Jonathan Rose},
title = {Effect of the prefabricated routing track distribution on {FPGA} area-efficiency},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {6},
number = {3},
pages = {445--456},
year = {1998},
url = {https://doi.org/10.1109/92.711315},
doi = {10.1109/92.711315},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BetzR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/KhalidR98,
author = {Mohammed A. S. Khalid and
Jonathan Rose},
editor = {Jason Cong and
Sinan Kaptanoglu},
title = {A Hybrid Complete-Graph Partial-Crossbar Routing Architecture for
Multi-FPGA Systems},
booktitle = {Proceedings of the 1998 {ACM/SIGDA} Sixth International Symposium
on Field Programmable Gate Arrays, {FPGA} 1998, Monterey, CA, USA,
February 22-24, 1998},
pages = {45--54},
publisher = {{ACM}},
year = {1998},
url = {https://doi.org/10.1145/275107.275119},
doi = {10.1145/275107.275119},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/KhalidR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/RoseKMSVT98,
author = {Jonathan Rose and
Sinan Kaptanoglu and
Clive McCarthy and
Rob Smith and
Sandip Vij and
Steve Taylor},
editor = {Jason Cong and
Sinan Kaptanoglu},
title = {Constraints from Hell: How to Tell Makes a Good {FPGA} (Panel)},
booktitle = {Proceedings of the 1998 {ACM/SIGDA} Sixth International Symposium
on Field Programmable Gate Arrays, {FPGA} 1998, Monterey, CA, USA,
February 22-24, 1998},
pages = {117--119},
publisher = {{ACM}},
year = {1998},
url = {https://doi.org/10.1145/275107.275127},
doi = {10.1145/275107.275127},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/RoseKMSVT98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/SwartzBR98,
author = {Jordan S. Swartz and
Vaughn Betz and
Jonathan Rose},
editor = {Jason Cong and
Sinan Kaptanoglu},
title = {A Fast Routability-Driven Router for FPGAs},
booktitle = {Proceedings of the 1998 {ACM/SIGDA} Sixth International Symposium
on Field Programmable Gate Arrays, {FPGA} 1998, Monterey, CA, USA,
February 22-24, 1998},
pages = {140--149},
publisher = {{ACM}},
year = {1998},
url = {https://doi.org/10.1145/275107.275134},
doi = {10.1145/275107.275134},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/SwartzBR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/WiltonRV97,
author = {Steven J. E. Wilton and
Jonathan Rose and
Zvonko G. Vranesic},
editor = {Carl Ebeling},
title = {Memory-to-Memory Connection Structures in FPGAs with Embedded Memory
Arrays},
booktitle = {Proceedings of the 1997 {ACM/SIGDA} Fifth International Symposium
on Field Programmable Gate Arrays, {FPGA} 1997, Monterey, CA, USA,
February 9-11, 1997},
pages = {10--16},
publisher = {{ACM}},
year = {1997},
url = {https://doi.org/10.1145/258305.258307},
doi = {10.1145/258305.258307},
timestamp = {Tue, 06 Nov 2018 16:58:23 +0100},
biburl = {https://dblp.org/rec/conf/fpga/WiltonRV97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LewisGIRC97,
author = {David M. Lewis and
David R. Galloway and
Marcus van Ierssel and
Jonathan Rose and
Paul Chow},
editor = {Carl Ebeling},
title = {The Transmogrifier-2: {A} 1 Million Gate Rapid Prototyping System},
booktitle = {Proceedings of the 1997 {ACM/SIGDA} Fifth International Symposium
on Field Programmable Gate Arrays, {FPGA} 1997, Monterey, CA, USA,
February 9-11, 1997},
pages = {53--61},
publisher = {{ACM}},
year = {1997},
url = {https://doi.org/10.1145/258305.258312},
doi = {10.1145/258305.258312},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LewisGIRC97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/RoseH97,
author = {Jonathan Rose and
Dwight D. Hill},
editor = {Carl Ebeling},
title = {Architectural and Physical Design Challenges for One-Million Gate
FPGAs and Beyond},
booktitle = {Proceedings of the 1997 {ACM/SIGDA} Fifth International Symposium
on Field Programmable Gate Arrays, {FPGA} 1997, Monterey, CA, USA,
February 9-11, 1997},
pages = {129--132},
publisher = {{ACM}},
year = {1997},
url = {https://doi.org/10.1145/258305.258324},
doi = {10.1145/258305.258324},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/RoseH97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/HuttonRC97,
author = {Michael D. Hutton and
Jonathan Rose and
Derek G. Corneil},
editor = {Carl Ebeling},
title = {Generation of Synthetic Sequential Benchmark Circuits},
booktitle = {Proceedings of the 1997 {ACM/SIGDA} Fifth International Symposium
on Field Programmable Gate Arrays, {FPGA} 1997, Monterey, CA, USA,
February 9-11, 1997},
pages = {149--155},
publisher = {{ACM}},
year = {1997},
url = {https://doi.org/10.1145/258305.258333},
doi = {10.1145/258305.258333},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/HuttonRC97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/BetzR97,
author = {Vaughn Betz and
Jonathan Rose},
editor = {Wayne Luk and
Peter Y. K. Cheung and
Manfred Glesner},
title = {{VPR:} {A} new packing, placement and routing tool for {FPGA} research},
booktitle = {Field-Programmable Logic and Applications, 7th International Workshop,
{FPL} '97, London, UK, September 1-3, 1997, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1304},
pages = {213--222},
publisher = {Springer},
year = {1997},
url = {https://doi.org/10.1007/3-540-63465-7\_226},
doi = {10.1007/3-540-63465-7\_226},
timestamp = {Tue, 14 May 2019 10:00:48 +0200},
biburl = {https://dblp.org/rec/conf/fpl/BetzR97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/BrownR96,
author = {Stephen Dean Brown and
Jonathan Rose},
title = {{FPGA} and {CPLD} Architectures: {A} Tutorial},
journal = {{IEEE} Des. Test Comput.},
volume = {13},
number = {2},
pages = {42--57},
year = {1996},
url = {https://doi.org/10.1109/54.500200},
doi = {10.1109/54.500200},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/BrownR96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/HuttonGRC96,
author = {Michael D. Hutton and
Jerry P. Grossman and
Jonathan Rose and
Derek G. Corneil},
editor = {Thomas Pennino and
Ellen J. Yoffa},
title = {Characterization and Parameterized Random Generation of Digital Circuits},
booktitle = {Proceedings of the 33st Conference on Design Automation, Las Vegas,
Nevada, USA, Las Vegas Convention Center, June 3-7, 1996},
pages = {94--99},
publisher = {{ACM} Press},
year = {1996},
url = {https://doi.org/10.1145/240518.240537},
doi = {10.1145/240518.240537},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/HuttonGRC96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/BetzR96,
author = {Vaughn Betz and
Jonathan Rose},
editor = {Rob A. Rutenbar and
Ralph H. J. M. Otten},
title = {Directional bias and non-uniformity in {FPGA} global routing architectures},
booktitle = {Proceedings of the 1996 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 1996, San Jose, CA, USA, November 10-14, 1996},
pages = {652--659},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1996},
url = {https://doi.org/10.1109/ICCAD.1996.571342},
doi = {10.1109/ICCAD.1996.571342},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/BetzR96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/fpga/1996,
editor = {Jonathan Rose and
Carl Ebeling},
title = {Proceedings of the 1996 Fourth International Symposium on Field Programmable
Gate Arrays, {FPGA} 1996, Monterey, CA, USA, February 11-13, 1996},
publisher = {{ACM}},
year = {1996},
url = {https://doi.org/10.1145/228370},
doi = {10.1145/228370},
isbn = {0-89791-773-1},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/1996.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/BetzR95,
author = {Vaughn Betz and
Jonathan Rose},
editor = {Pak K. Chan and
Jonathan Rose},
title = {Using Architectural "Families" to Increase {FPGA} Speed
and Density},
booktitle = {Proceedings of the Third International {ACM} Symposium on Field-Programmable
Gate Arrays,FPGA 1995, Monterey, California, USA, February 12-14,
1995},
pages = {10--16},
publisher = {{ACM}},
year = {1995},
url = {https://doi.org/10.1145/201310.201312},
doi = {10.1145/201310.201312},
timestamp = {Tue, 06 Nov 2018 16:58:23 +0100},
biburl = {https://dblp.org/rec/conf/fpga/BetzR95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/WiltonRV95,
author = {Steven J. E. Wilton and
Jonathan Rose and
Zvonko G. Vranesic},
editor = {Pak K. Chan and
Jonathan Rose},
title = {Architecture of Centralized Field-Configurable Memory},
booktitle = {Proceedings of the Third International {ACM} Symposium on Field-Programmable
Gate Arrays,FPGA 1995, Monterey, California, USA, February 12-14,
1995},
pages = {97--103},
publisher = {{ACM}},
year = {1995},
url = {https://doi.org/10.1145/201310.201326},
doi = {10.1145/201310.201326},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/WiltonRV95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/fpga/1995,
editor = {Pak K. Chan and
Jonathan Rose},
title = {Proceedings of the Third International {ACM} Symposium on Field-Programmable
Gate Arrays,FPGA 1995, Monterey, California, USA, February 12-14,
1995},
publisher = {{ACM}},
year = {1995},
url = {https://doi.org/10.1145/201310},
doi = {10.1145/201310},
isbn = {0-89791-743-X},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/1995.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/KarchmerR94,
author = {David Karchmer and
Jonathan Rose},
editor = {Jochen A. G. Jess and
Richard L. Rudell},
title = {Definition and solution of the memory packing problem for field-programmable
systems},
booktitle = {Proceedings of the 1994 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 1994, San Jose, California, USA, November 6-10, 1994},
pages = {20--26},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1994},
url = {https://doi.org/10.1109/ICCAD.1994.629737},
doi = {10.1109/ICCAD.1994.629737},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/KarchmerR94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/pieee/RoseGS93,
author = {Jonathan Rose and
Abbas El Gamal and
Alberto L. Sangiovanni{-}Vincentelli},
title = {Architecture of field-programmable gate arrays},
journal = {Proc. {IEEE}},
volume = {81},
number = {7},
pages = {1013--1029},
year = {1993},
url = {https://doi.org/10.1109/5.231340},
doi = {10.1109/5.231340},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/pieee/RoseGS93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/pieee/Sangiovanni-Vincentelli93,
author = {Alberto L. Sangiovanni{-}Vincentelli and
Abbas El Gamal and
Jonathan Rose},
title = {Synthesis method for field programmable gate arrays},
journal = {Proc. {IEEE}},
volume = {81},
number = {7},
pages = {1057--1083},
year = {1993},
url = {https://doi.org/10.1109/5.231344},
doi = {10.1109/5.231344},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/pieee/Sangiovanni-Vincentelli93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BrownRV93,
author = {Stephen Dean Brown and
Jonathan Rose and
Zvonko G. Vranesic},
title = {A stochastic model to predict the routability of field-programmable
gate arrays},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {12},
number = {12},
pages = {1827--1838},
year = {1993},
url = {https://doi.org/10.1109/43.251146},
doi = {10.1109/43.251146},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BrownRV93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/Rose93,
author = {Jonathan Rose},
editor = {Alfred E. Dunlop},
title = {Logic Emulation: {A} Niche or a Future Standard for Design Verification?
(Panel Abstract)},
booktitle = {Proceedings of the 30th Design Automation Conference. Dallas, Texas,
USA, June 14-18, 1993},
pages = {164},
publisher = {{ACM} Press},
year = {1993},
url = {https://doi.org/10.1145/157485.164649},
doi = {10.1145/157485.164649},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/Rose93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BrownRV92,
author = {Stephen Dean Brown and
Jonathan Rose and
Zvonko G. Vranesic},
title = {A detailed router for field-programmable gate arrays},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {11},
number = {5},
pages = {620--628},
year = {1992},
url = {https://doi.org/10.1109/43.127623},
doi = {10.1109/43.127623},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BrownRV92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ChungR92,
author = {Kevin Chung and
Jonathan Rose},
editor = {Daniel G. Schweikert},
title = {{TEMPT:} Technology Mapping for the Exploration of {FPGA} Architectures
with Hard-Wired Connections},
booktitle = {Proceedings of the 29th Design Automation Conference, Anaheim, California,
USA, June 8-12, 1992},
pages = {361--367},
publisher = {{IEEE} Computer Society Press},
year = {1992},
url = {http://portal.acm.org/citation.cfm?id=113938.149490},
timestamp = {Thu, 16 Mar 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ChungR92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/TsengRB92,
author = {Benjamin Tseng and
Jonathan Rose and
Stephen Dean Brown},
title = {Improving {FPGA} Routing Architectures Using Architecture and {CAD}
Interactions},
booktitle = {Proceedings 1992 {IEEE} International Conference on Computer Design:
{VLSI} in Computer {\&} Processors, {ICCD} '92, Cambridge, MA,
USA, October 11-14, 1992},
pages = {99--104},
publisher = {{IEEE} Computer Society},
year = {1992},
url = {https://doi.org/10.1109/ICCD.1992.276198},
doi = {10.1109/ICCD.1992.276198},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/TsengRB92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/FrancisRV91,
author = {Robert J. Francis and
Jonathan Rose and
Zvonko G. Vranesic},
editor = {A. Richard Newton},
title = {Chortle-crf: Fast Technology Mapping for Lookup Table-Based FPGAs},
booktitle = {Proceedings of the 28th Design Automation Conference, San Francisco,
California, USA, June 17-21, 1991},
pages = {227--233},
publisher = {{ACM}},
year = {1991},
url = {https://doi.org/10.1145/127601.127670},
doi = {10.1145/127601.127670},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/FrancisRV91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/Rose91,
author = {Jonathan Rose},
editor = {A. Richard Newton},
title = {Will the Field-Programmable Gata Array Replace the Mask-Programmable
Gate Array? (Panel Abstract)},
booktitle = {Proceedings of the 28th Design Automation Conference, San Francisco,
California, USA, June 17-21, 1991},
pages = {779},
publisher = {{ACM}},
year = {1991},
timestamp = {Thu, 16 Mar 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/Rose91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/FrancisRV91,
author = {Robert J. Francis and
Jonathan Rose and
Zvonko G. Vranesic},
title = {Technology Mapping on Lookup Table-Based FPGAs for Performance},
booktitle = {1991 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 1993, Santa Clara, CA, USA, November 11-14, 1991. Digest of
Technical Papers},
pages = {568--571},
publisher = {{IEEE} Computer Society},
year = {1991},
url = {https://doi.org/10.1109/ICCAD.1991.185334},
doi = {10.1109/ICCAD.1991.185334},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/FrancisRV91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RoseKW90,
author = {Jonathan Rose and
Wolfgang Klebsch and
J{\"{u}}rgen Wolf},
title = {Temperature measurement and equilibrium dynamics of simulated annealing
placements},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {3},
pages = {253--259},
year = {1990},
url = {https://doi.org/10.1109/43.46801},
doi = {10.1109/43.46801},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RoseKW90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Rose90,
author = {Jonathan Rose},
title = {Parallel global routing for standard cells},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {9},
number = {10},
pages = {1085--1095},
year = {1990},
url = {https://doi.org/10.1109/43.62733},
doi = {10.1109/43.62733},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Rose90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/FrancisRC90,
author = {Robert J. Francis and
Jonathan Rose and
Kevin Chung},
editor = {Richard C. Smith},
title = {Chortle: {A} Technology Mapping Program for Lookup Table-Based Field
Programmable Gate Arrays},
booktitle = {Proceedings of the 27th {ACM/IEEE} Design Automation Conference. Orlando,
Florida, USA, June 24-28, 1990},
pages = {613--619},
publisher = {{IEEE} Computer Society Press},
year = {1990},
url = {https://doi.org/10.1145/123186.123418},
doi = {10.1145/123186.123418},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/FrancisRC90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/BrownRV90,
author = {Stephen Dean Brown and
Jonathan Rose and
Zvonko G. Vranesic},
title = {A Detailed Router for Field-Programmable Gate Arrays},
booktitle = {{IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD}
1990, Santa Clara, CA, USA, November 11-15, 1990. Digest of Technical
Papers},
pages = {382--385},
publisher = {{IEEE} Computer Society},
year = {1990},
url = {https://doi.org/10.1109/ICCAD.1990.129931},
doi = {10.1109/ICCAD.1990.129931},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/BrownRV90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RoseSV88,
author = {Jonathan Rose and
W. Martin Snelgrove and
Zvonko G. Vranesic},
title = {Parallel standard cell placement algorithms with quality equivalent
to simulated annealing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {7},
number = {3},
pages = {387--396},
year = {1988},
url = {https://doi.org/10.1109/43.3172},
doi = {10.1109/43.3172},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RoseSV88.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/Rose88,
author = {Jonathan Rose},
editor = {Dennis W. Shaklee and
A. Richard Newton},
title = {LocusRoute: {A} Parallel Global Router for Standard Cells},
booktitle = {Proceedings of the 25th {ACM/IEEE} Conference on Design Automation,
{DAC} '88, Anaheim, CA, USA, June 12-15, 1988},
pages = {189--195},
publisher = {{ACM}},
year = {1988},
url = {http://portal.acm.org/citation.cfm?id=285730.285762},
timestamp = {Fri, 12 Mar 2021 15:27:48 +0100},
biburl = {https://dblp.org/rec/conf/dac/Rose88.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/RoseKW88,
author = {Jonathan Rose and
Wolfgang Klebsch and
J{\"{u}}rgen Wolf},
title = {Temperature measurement of simulated annealing placements},
booktitle = {1988 {IEEE} International Conference on Computer-Aided Design, {ICCAD}
1988, Santa Clara, CA, USA, November 7-10, 1988. Digest of Technical
Papers},
pages = {514--517},
publisher = {{IEEE} Computer Society},
year = {1988},
url = {https://doi.org/10.1109/ICCAD.1988.122561},
doi = {10.1109/ICCAD.1988.122561},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/RoseKW88.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ppopp/Rose88,
author = {Jonathan Rose},
editor = {Richard L. Wexelblat},
title = {The Parallel Decomposition and Implementation of an Integrated Circuit
Global Router},
booktitle = {Proceedings of the {ACM/SIGPLAN} {PPEALS} 1988, Parallel Programming:
Experience with Applications, Languages and Systems, New Haven, Connecticut,
USA, July 19-21, 1988},
pages = {138--145},
publisher = {{ACM}},
year = {1988},
url = {https://doi.org/10.1145/62115.62129},
doi = {10.1145/62115.62129},
timestamp = {Sun, 12 Jun 2022 19:46:08 +0200},
biburl = {https://dblp.org/rec/conf/ppopp/Rose88.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/RoseLV85,
author = {Jonathan Rose and
Wayne M. Loucks and
Zvonko G. Vranesic},
title = {{FERMTOR:} {A} Tunable Multiprocessor Architecture},
journal = {{IEEE} Micro},
volume = {5},
number = {4},
pages = {5--17},
year = {1985},
url = {https://doi.org/10.1109/MM.1985.304476},
doi = {10.1109/MM.1985.304476},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/micro/RoseLV85.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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