BibTeX records: Yuji Oda

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@article{DBLP:journals/jssc/OhbayashiYKOIUY08,
  author       = {Shigeki Ohbayashi and
                  Makoto Yabuuchi and
                  Kazushi Kono and
                  Yuji Oda and
                  Susumu Imaoka and
                  Keiichi Usui and
                  Toshiaki Yonezu and
                  Takeshi Iwamoto and
                  Koji Nii and
                  Yasumasa Tsukamoto and
                  Masashi Arakawa and
                  Takahiro Uchida and
                  Masakazu Okada and
                  Atsushi Ishii and
                  Tsutomu Yoshihara and
                  Hiroshi Makino and
                  Koichiro Ishibashi and
                  Hirofumi Shinohara},
  title        = {A 65 nm Embedded {SRAM} With Wafer Level Burn-In Mode, Leak-Bit Redundancy
                  and Cu E-Trim Fuse for Known Good Die},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {43},
  number       = {1},
  pages        = {96--108},
  year         = {2008},
  url          = {https://doi.org/10.1109/JSSC.2007.908004},
  doi          = {10.1109/JSSC.2007.908004},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/OhbayashiYKOIUY08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/OhbayashiYNTIOY07,
  author       = {Shigeki Ohbayashi and
                  Makoto Yabuuchi and
                  Koji Nii and
                  Yasumasa Tsukamoto and
                  Susumu Imaoka and
                  Yuji Oda and
                  Tsutomu Yoshihara and
                  Motoshige Igarashi and
                  Masahiko Takeuchi and
                  Hiroshi Kawashima and
                  Yasuo Yamaguchi and
                  Kazuhiro Tsukamoto and
                  Masahide Inuishi and
                  Hiroshi Makino and
                  Koichiro Ishibashi and
                  Hirofumi Shinohara},
  title        = {A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read
                  and Write Operation Stabilizing Circuits},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {42},
  number       = {4},
  pages        = {820--829},
  year         = {2007},
  url          = {https://doi.org/10.1109/JSSC.2007.891648},
  doi          = {10.1109/JSSC.2007.891648},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/OhbayashiYNTIOY07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/OhbayashiYKOIUYINTAUOIMIS07,
  author       = {Shigeki Ohbayashi and
                  Makoto Yabuuchi and
                  Kazushi Kono and
                  Yuji Oda and
                  Susumu Imaoka and
                  Keiichi Usui and
                  Toshiaki Yonezu and
                  Takeshi Iwamoto and
                  Koji Nii and
                  Yasumasa Tsukamoto and
                  Masashi Arakawa and
                  Takahiro Uchida and
                  Masakazu Okada and
                  Atsushi Ishii and
                  Hiroshi Makino and
                  Koichiro Ishibashi and
                  Hirofumi Shinohara},
  title        = {A 65nm Embedded {SRAM} with Wafer-Level Burn-In Mode, Leak-Bit Redundancy
                  and E-Trim Fuse for Known Good Die},
  booktitle    = {2007 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2007, Digest of Technical Papers, San Francisco, CA, USA, February
                  11-15, 2007},
  pages        = {488--617},
  publisher    = {{IEEE}},
  year         = {2007},
  url          = {https://doi.org/10.1109/ISSCC.2007.373507},
  doi          = {10.1109/ISSCC.2007.373507},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/OhbayashiYKOIUYINTAUOIMIS07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iccad/TsukamotoNIOOYMIS05,
  author       = {Yasumasa Tsukamoto and
                  Koji Nii and
                  Susumu Imaoka and
                  Yuji Oda and
                  Shigeki Ohbayashi and
                  Tomoaki Yoshizawa and
                  Hiroshi Makino and
                  Koichiro Ishibashi and
                  Hirofumi Shinohara},
  title        = {Worst-case analysis to obtain stable read/write {DC} margin of high
                  density 6T-SRAM-array with local Vth variability},
  booktitle    = {2005 International Conference on Computer-Aided Design, {ICCAD} 2005,
                  San Jose, CA, USA, November 6-10, 2005},
  pages        = {398--405},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ICCAD.2005.1560101},
  doi          = {10.1109/ICCAD.2005.1560101},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/iccad/TsukamotoNIOOYMIS05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}