BibTeX records: Shigetoshi Nakatake

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@article{DBLP:journals/ieicet/KondoTTN18,
  author    = {Kenya Kondo and
               Koichi Tanno and
               Hiroki Tamura and
               Shigetoshi Nakatake},
  title     = {Low Voltage {CMOS} Current Mode Reference Circuit without Operational
               Amplifiers},
  journal   = {{IEICE} Transactions},
  volume    = {101-A},
  number    = {5},
  pages     = {748--754},
  year      = {2018},
  url       = {https://doi.org/10.1587/transfun.E101.A.748},
  doi       = {10.1587/transfun.E101.A.748},
  timestamp = {Thu, 27 Sep 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/ieicet/KondoTTN18},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/IshiguchiION18,
  author    = {Yoritaka Ishiguchi and
               Daishi Isogai and
               Takuma Osawa and
               Shigetoshi Nakatake},
  title     = {Analog perceptron circuit with DAC-based multiplier},
  journal   = {Integration},
  volume    = {63},
  pages     = {240--247},
  year      = {2018},
  url       = {https://doi.org/10.1016/j.vlsi.2018.05.010},
  doi       = {10.1016/j.vlsi.2018.05.010},
  timestamp = {Fri, 26 Oct 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/integration/IshiguchiION18},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LiuCYN18,
  author    = {Bo Liu and
               Gong Chen and
               Bo Yang and
               Shigetoshi Nakatake},
  title     = {Routable and Matched Layout Styles for Analog Module Generation},
  journal   = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume    = {23},
  number    = {4},
  pages     = {47:1--47:17},
  year      = {2018},
  url       = {https://doi.org/10.1145/3182169},
  doi       = {10.1145/3182169},
  timestamp = {Wed, 21 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/journals/todaes/LiuCYN18},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mwscas/ShirakawaSN18,
  author    = {Takaaki Shirakawa and
               Ryosuke Sakai and
               Shigetoshi Nakatake},
  title     = {On-chip Impedance Evaluation with Auto-calibration based on Auto-balancing
               Bridge},
  booktitle = {{IEEE} 61st International Midwest Symposium on Circuits and Systems,
               {MWSCAS} 2018, Windsor, ON, Canada, August 5-8, 2018},
  pages     = {262--265},
  year      = {2018},
  crossref  = {DBLP:conf/mwscas/2018},
  url       = {https://doi.org/10.1109/MWSCAS.2018.8623881},
  doi       = {10.1109/MWSCAS.2018.8623881},
  timestamp = {Wed, 17 Apr 2019 09:51:21 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/mwscas/ShirakawaSN18},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ngcas/GengN18,
  author    = {Chao Geng and
               Shigetoshi Nakatake},
  title     = {Hierarchical Floorplanning Based on Analog Structure Tree},
  booktitle = {2018 New Generation of CAS, {NGCAS} 2018, Valletta, Malta, November
               20-23, 2018},
  pages     = {138--141},
  year      = {2018},
  crossref  = {DBLP:conf/ngcas/2018},
  url       = {https://doi.org/10.1109/NGCAS.2018.8572241},
  doi       = {10.1109/NGCAS.2018.8572241},
  timestamp = {Thu, 20 Dec 2018 09:01:24 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/ngcas/GengN18},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ngcas/ZouN18,
  author    = {Xuncheng Zou and
               Shigetoshi Nakatake},
  title     = {Analog Retargeting Constraint Extraction Based on Fundamental Circuits
               and Layout Regularity},
  booktitle = {2018 New Generation of CAS, {NGCAS} 2018, Valletta, Malta, November
               20-23, 2018},
  pages     = {142--145},
  year      = {2018},
  crossref  = {DBLP:conf/ngcas/2018},
  url       = {https://doi.org/10.1109/NGCAS.2018.8572209},
  doi       = {10.1109/NGCAS.2018.8572209},
  timestamp = {Thu, 20 Dec 2018 09:01:24 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/ngcas/ZouN18},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ZouLN17,
  author    = {Xuncheng Zou and
               Bo Liu and
               Shigetoshi Nakatake},
  title     = {Low Voltage Stochastic Flash {ADC} with Front-end of Inverter-based
               Comparative Unit},
  booktitle = {Proceedings of the on Great Lakes Symposium on {VLSI} 2017, Banff,
               AB, Canada, May 10-12, 2017},
  pages     = {435--438},
  year      = {2017},
  crossref  = {DBLP:conf/glvlsi/2017},
  url       = {https://doi.org/10.1145/3060403.3060466},
  doi       = {10.1145/3060403.3060466},
  timestamp = {Tue, 06 Nov 2018 16:59:34 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/glvlsi/ZouLN17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/KimHLN17,
  author    = {Myung{-}Chul Kim and
               Shih{-}Hsu Huang and
               Rung{-}Bin Lin and
               Shigetoshi Nakatake},
  title     = {Overview of the 2017 {CAD} contest at {ICCAD:} Invited paper},
  booktitle = {2017 {IEEE/ACM} International Conference on Computer-Aided Design,
               {ICCAD} 2017, Irvine, CA, USA, November 13-16, 2017},
  pages     = {855--856},
  year      = {2017},
  crossref  = {DBLP:conf/iccad/2017},
  url       = {https://doi.org/10.1109/ICCAD.2017.8203867},
  doi       = {10.1109/ICCAD.2017.8203867},
  timestamp = {Mon, 09 Apr 2018 15:38:24 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iccad/KimHLN17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ngcas/IshiguchiION17,
  author    = {Yoritaka Ishiguchi and
               Daishi Isogai and
               Takuma Osawa and
               Shigetoshi Nakatake},
  title     = {A Perceptron Circuit with DAC-Based Multiplier for Sensor Analog Front-Ends},
  booktitle = {New Generation of CAS, {NGCAS} 2017, Genova, Italy, September 6-9,
               2017},
  pages     = {93--96},
  year      = {2017},
  crossref  = {DBLP:conf/ngcas/2017},
  url       = {https://doi.org/10.1109/NGCAS.2017.23},
  doi       = {10.1109/NGCAS.2017.23},
  timestamp = {Fri, 27 Oct 2017 14:04:25 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/ngcas/IshiguchiION17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ngcas/IsogaiLIN17,
  author    = {Daishi Isogai and
               Bo Liu and
               Yoritaka Ishiguchi and
               Shigetoshi Nakatake},
  title     = {Analog Characterization Module with Data Converter-Coupled Signal
               Reconfiguration},
  booktitle = {New Generation of CAS, {NGCAS} 2017, Genova, Italy, September 6-9,
               2017},
  pages     = {149--152},
  year      = {2017},
  crossref  = {DBLP:conf/ngcas/2017},
  url       = {https://doi.org/10.1109/NGCAS.2017.35},
  doi       = {10.1109/NGCAS.2017.35},
  timestamp = {Fri, 27 Oct 2017 14:04:25 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/ngcas/IsogaiLIN17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/GohN16,
  author    = {Chooi{-}Ling Goh and
               Shigetoshi Nakatake},
  title     = {A Sensor-Based Data Visualization System for Training Blood Pressure
               Measurement by Auscultatory Method},
  journal   = {{IEICE} Transactions},
  volume    = {99-D},
  number    = {4},
  pages     = {936--943},
  year      = {2016},
  url       = {https://doi.org/10.1587/transinf.2015DAP0010},
  doi       = {10.1587/transinf.2015DAP0010},
  timestamp = {Thu, 27 Sep 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/ieicet/GohN16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/HirataNNSMMTY16,
  author    = {Takuya Hirata and
               Ryuta Nishino and
               Shigetoshi Nakatake and
               Masaya Shimoyama and
               Masashi Miyagawa and
               Ryoichi Miyauchi and
               Koichi Tanno and
               Akihiro Yamada},
  title     = {Subblock-Level Matching Layout for Analog Block-Pair and Its Layout-Dependent
               Manufacturability Evaluation},
  journal   = {{IEICE} Transactions},
  volume    = {99-A},
  number    = {7},
  pages     = {1381--1389},
  year      = {2016},
  url       = {https://doi.org/10.1587/transfun.E99.A.1381},
  doi       = {10.1587/transfun.E99.A.1381},
  timestamp = {Thu, 27 Sep 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/ieicet/HirataNNSMMTY16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/ChenFDNY16,
  author    = {Gong Chen and
               Toru Fujimura and
               Qing Dong and
               Shigetoshi Nakatake and
               Bo Yang},
  title     = {{DC} Characteristics and Variability on 90nm {CMOS} Transistor Array-Style
               Analog Layout},
  journal   = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume    = {21},
  number    = {3},
  pages     = {45:1--45:21},
  year      = {2016},
  url       = {https://doi.org/10.1145/2888395},
  doi       = {10.1145/2888395},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/journals/todaes/ChenFDNY16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/HuangLKN16,
  author    = {Shih{-}Hsu Huang and
               Rung{-}Bin Lin and
               Myung{-}Chul Kim and
               Shigetoshi Nakatake},
  title     = {Overview of the 2016 {CAD} contest at {ICCAD}},
  booktitle = {Proceedings of the 35th International Conference on Computer-Aided
               Design, {ICCAD} 2016, Austin, TX, USA, November 7-10, 2016},
  pages     = {38},
  year      = {2016},
  crossref  = {DBLP:conf/iccad/2016},
  url       = {https://doi.org/10.1145/2966986.2980070},
  doi       = {10.1145/2966986.2980070},
  timestamp = {Tue, 06 Nov 2018 11:07:08 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/iccad/HuangLKN16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/LiuNYC16,
  author    = {Bo Liu and
               Shigetoshi Nakatake and
               Bo Yang and
               Gong Chen},
  title     = {Twin-row-style for {MOS} analog layout},
  booktitle = {2016 {IEEE} International Conference on Electronics, Circuits and
               Systems, {ICECS} 2016, Monte Carlo, Monaco, December 11-14, 2016},
  pages     = {141--144},
  year      = {2016},
  crossref  = {DBLP:conf/icecsys/2016},
  url       = {https://doi.org/10.1109/ICECS.2016.7841152},
  doi       = {10.1109/ICECS.2016.7841152},
  timestamp = {Tue, 23 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/icecsys/LiuNYC16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/YahiroLNNTC16,
  author    = {Nobuyuki Yahiro and
               Bo Liu and
               Atsushi Nanri and
               Shigetoshi Nakatake and
               Yasuhiro Takashima and
               Gong Chen},
  title     = {A multi-functional memory unit with PLA-based reconfigurable decoder},
  booktitle = {International Conference on ReConFigurable Computing and FPGAs, ReConFig
               2016, Cancun, Mexico, November 30 - Dec. 2, 2016},
  pages     = {1--7},
  year      = {2016},
  crossref  = {DBLP:conf/reconfig/2016},
  url       = {https://doi.org/10.1109/ReConFig.2016.7857145},
  doi       = {10.1109/ReConFig.2016.7857145},
  timestamp = {Sun, 21 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/reconfig/YahiroLNNTC16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/ChenZDLN15,
  author    = {Gong Chen and
               Yu Zhang and
               Qing Dong and
               Mingyu Li and
               Shigetoshi Nakatake},
  title     = {Layout Dependent Effect-Aware Leakage Current Reduction and Its Application
               to Low-Power {SAR-ADC}},
  journal   = {{IEICE} Transactions},
  volume    = {98-A},
  number    = {7},
  pages     = {1442--1454},
  year      = {2015},
  url       = {https://doi.org/10.1587/transfun.E98.A.1442},
  doi       = {10.1587/transfun.E98.A.1442},
  timestamp = {Fri, 28 Sep 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/ieicet/ChenZDLN15},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/HirataNNSMTY15,
  author    = {Takuya Hirata and
               Ryuta Nishino and
               Shigetoshi Nakatake and
               Masaya Shimoyama and
               Masashi Miyagawa and
               Koichi Tanno and
               Akihiro Yamada},
  title     = {Subblock-level matching layout for analog block-pair and its manufacturability
               evaluation},
  booktitle = {2015 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
               2015, Lisbon, Portugal, May 24-27, 2015},
  pages     = {3012--3015},
  year      = {2015},
  crossref  = {DBLP:conf/iscas/2015},
  url       = {https://doi.org/10.1109/ISCAS.2015.7169321},
  doi       = {10.1109/ISCAS.2015.7169321},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iscas/HirataNNSMTY15},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/MurookaZDN15,
  author    = {Daijiro Murooka and
               Yu Zhang and
               Qing Dong and
               Shigetoshi Nakatake},
  title     = {Low-Power and Low-Variability Programmable Delay Element and Its Application
               to Post-Silicon Skew Tuning},
  booktitle = {2015 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2015,
               Montpellier, France, July 8-10, 2015},
  pages     = {167--171},
  year      = {2015},
  crossref  = {DBLP:conf/isvlsi/2015},
  url       = {https://doi.org/10.1109/ISVLSI.2015.91},
  doi       = {10.1109/ISVLSI.2015.91},
  timestamp = {Tue, 22 May 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isvlsi/MurookaZDN15},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/YangDLN13,
  author    = {Bo Yang and
               Qing Dong and
               Jing Li and
               Shigetoshi Nakatake},
  title     = {Structured Analog Circuit and Layout Design with Transistor Array},
  journal   = {{IEICE} Transactions},
  volume    = {96-A},
  number    = {12},
  pages     = {2475--2486},
  year      = {2013},
  url       = {https://doi.org/10.1587/transfun.E96.A.2475},
  doi       = {10.1587/transfun.E96.A.2475},
  timestamp = {Fri, 28 Sep 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/ieicet/YangDLN13},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/ZhangCYLDLN13,
  author    = {Yu Zhang and
               Gong Chen and
               Bo Yang and
               Jing Li and
               Qing Dong and
               Mingyu Li and
               Shigetoshi Nakatake},
  title     = {Analog Circuit Synthesis with Constraint Generation of Layout-Dependent
               Effects by Geometric Programming},
  journal   = {{IEICE} Transactions},
  volume    = {96-A},
  number    = {12},
  pages     = {2487--2498},
  year      = {2013},
  url       = {https://doi.org/10.1587/transfun.E96.A.2487},
  doi       = {10.1587/transfun.E96.A.2487},
  timestamp = {Fri, 28 Sep 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/ieicet/ZhangCYLDLN13},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ChenYZDN13,
  author    = {Gong Chen and
               Bo Yang and
               Yu Zhang and
               Qing Dong and
               Shigetoshi Nakatake},
  title     = {A 9-bit 50msps {SAR} {ADC} with pre-charge {VCM} -based double input
               range algorithm},
  booktitle = {Great Lakes Symposium on {VLSI} 2013 (part of ECRC), GLSVLSI'13, Paris,
               France, May 2-4, 2013},
  pages     = {315--316},
  year      = {2013},
  crossref  = {DBLP:conf/glvlsi/2013},
  url       = {https://doi.org/10.1145/2483028.2483119},
  doi       = {10.1145/2483028.2483119},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/glvlsi/ChenYZDN13},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/Nakatake13,
  author    = {Shigetoshi Nakatake},
  title     = {Practicality on placement given by optimality of packing},
  booktitle = {International Symposium on Physical Design, ISPD'13, Stateline, NV,
               USA, March 24-27, 2013},
  pages     = {59--60},
  year      = {2013},
  crossref  = {DBLP:conf/ispd/2013},
  url       = {https://doi.org/10.1145/2451916.2451931},
  doi       = {10.1145/2451916.2451931},
  timestamp = {Tue, 06 Nov 2018 11:07:47 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/ispd/Nakatake13},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ChenZYDN13,
  author    = {Gong Chen and
               Yu Zhang and
               Bo Yang and
               Qing Dong and
               Shigetoshi Nakatake},
  title     = {A comparator energy model considering shallow trench isolation stress
               by geometric programming},
  booktitle = {International Symposium on Quality Electronic Design, {ISQED} 2013,
               Santa Clara, CA, USA, March 4-6, 2013},
  pages     = {585--590},
  year      = {2013},
  crossref  = {DBLP:conf/isqed/2013},
  url       = {https://doi.org/10.1109/ISQED.2013.6523670},
  doi       = {10.1109/ISQED.2013.6523670},
  timestamp = {Tue, 22 May 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isqed/ChenZYDN13},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhangCDLN13,
  author    = {Yu Zhang and
               Gong Chen and
               Qing Dong and
               Mingyu Li and
               Shigetoshi Nakatake},
  title     = {Performance-driven {SRAM} macro design with parameterized cell considering
               layout-dependent effects},
  booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
               VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
  pages     = {156--161},
  year      = {2013},
  crossref  = {DBLP:conf/vlsi/2013soc},
  url       = {https://doi.org/10.1109/VLSI-SoC.2013.6673268},
  doi       = {10.1109/VLSI-SoC.2013.6673268},
  timestamp = {Tue, 22 May 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/vlsi/ZhangCDLN13},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/LiuYN12,
  author    = {Bo Liu and
               Bo Yang and
               Shigetoshi Nakatake},
  title     = {Layout-Aware Variability Characterization of {CMOS} Current Sources},
  journal   = {{IEICE} Transactions},
  volume    = {95-C},
  number    = {4},
  pages     = {696--705},
  year      = {2012},
  url       = {https://doi.org/10.1587/transele.E95.C.696},
  doi       = {10.1587/transele.E95.C.696},
  timestamp = {Sat, 29 Sep 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/ieicet/LiuYN12},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChenYNHI12,
  author    = {Gong Chen and
               Bo Yang and
               Shigetoshi Nakatake and
               Zhangcai Huang and
               Yasuaki Inoue},
  title     = {A retargeting methodology of nano-watt {CMOS} reference circuit based
               on advanced compact {MOSFET} model},
  booktitle = {2012 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
               2012, Seoul, Korea (South), May 20-23, 2012},
  pages     = {938--941},
  year      = {2012},
  crossref  = {DBLP:conf/iscas/2012},
  url       = {https://doi.org/10.1109/ISCAS.2012.6272199},
  doi       = {10.1109/ISCAS.2012.6272199},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iscas/ChenYNHI12},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/ZhangLYLN12,
  author    = {Yu Zhang and
               Bo Liu and
               Bo Yang and
               Jing Li and
               Shigetoshi Nakatake},
  title     = {{CMOS} op-amp circuit synthesis with geometric programming models
               for layout-dependent effects},
  booktitle = {Thirteenth International Symposium on Quality Electronic Design, {ISQED}
               2012, Santa Clara, CA, USA, March 19-21, 2012},
  pages     = {464--469},
  year      = {2012},
  crossref  = {DBLP:conf/isqed/2012},
  url       = {https://doi.org/10.1109/ISQED.2012.6187534},
  doi       = {10.1109/ISQED.2012.6187534},
  timestamp = {Thu, 25 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isqed/ZhangLYLN12},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/DongYCLN12,
  author    = {Qing Dong and
               Bo Yang and
               Gong Chen and
               Jing Li and
               Shigetoshi Nakatake},
  title     = {Transistor channel decomposition for structured analog layout, manufacturability
               and low-power applications},
  booktitle = {Thirteenth International Symposium on Quality Electronic Design, {ISQED}
               2012, Santa Clara, CA, USA, March 19-21, 2012},
  pages     = {656--662},
  year      = {2012},
  crossref  = {DBLP:conf/isqed/2012},
  url       = {https://doi.org/10.1109/ISQED.2012.6187562},
  doi       = {10.1109/ISQED.2012.6187562},
  timestamp = {Tue, 22 May 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isqed/DongYCLN12},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ShinoharaHLDYN11,
  author    = {Kota Shinohara and
               Mihoko Hidaka and
               Jing Li and
               Qing Dong and
               Bo Yang and
               Shigetoshi Nakatake},
  title     = {Layout-aware variation evaluation of analog circuits and its validity
               on op-amp designs},
  booktitle = {Proceedings of the 21st {ACM} Great Lakes Symposium on {VLSI} 2010,
               Lausanne, Switzerland, May 2-6, 2011},
  pages     = {247--252},
  year      = {2011},
  crossref  = {DBLP:conf/glvlsi/2011},
  url       = {https://doi.org/10.1145/1973009.1973059},
  doi       = {10.1145/1973009.1973059},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/glvlsi/ShinoharaHLDYN11},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/LiuDYLN11,
  author    = {Bo Liu and
               Qing Dong and
               Bo Yang and
               Jing Li and
               Shigetoshi Nakatake},
  title     = {Layout-aware mismatch modeling for {CMOS} current sources with {D/A}
               converter analysis},
  booktitle = {Proceedings of the 12th International Symposium on Quality Electronic
               Design, {ISQED} 2011, Santa Clara, California, USA, 14-16 March 2011},
  pages     = {525--532},
  year      = {2011},
  crossref  = {DBLP:conf/isqed/2011},
  url       = {https://doi.org/10.1109/ISQED.2011.5770777},
  doi       = {10.1109/ISQED.2011.5770777},
  timestamp = {Tue, 22 May 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isqed/LiuDYLN11},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/NakatakeKIKKIH10,
  author    = {Shigetoshi Nakatake and
               Masahiro Kawakita and
               Takao Ito and
               Masahiro Kojima and
               Michiko Kojima and
               Kenji Izumi and
               Tadayuki Habasaki},
  title     = {Regularity-Oriented Analog Placement with Conditional Design Rules},
  journal   = {{IEICE} Transactions},
  volume    = {93-A},
  number    = {12},
  pages     = {2389--2398},
  year      = {2010},
  url       = {https://doi.org/10.1587/transfun.E93.A.2389},
  doi       = {10.1587/transfun.E93.A.2389},
  timestamp = {Sat, 29 Sep 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/ieicet/NakatakeKIKKIH10},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KatoEINYI10,
  author    = {Kokoro Kato and
               Masakazu Endo and
               Tadao Inoue and
               Shigetoshi Nakatake and
               Masaki Yamabe and
               Sunao Ishihara},
  title     = {Photomask Data Prioritization Based on {VLSI} Design Intent and Its
               Utilization for Mask Manufacturing},
  journal   = {{IEICE} Transactions},
  volume    = {93-A},
  number    = {12},
  pages     = {2424--2432},
  year      = {2010},
  url       = {https://doi.org/10.1587/transfun.E93.A.2424},
  doi       = {10.1587/transfun.E93.A.2424},
  timestamp = {Sat, 29 Sep 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/ieicet/KatoEINYI10},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/NakatakeKIKKIH10,
  author    = {Shigetoshi Nakatake and
               Masahiro Kawakita and
               Takao Ito and
               Masahiro Kojima and
               Michiko Kojima and
               Kenji Izumi and
               Tadayuki Habasaki},
  title     = {Regularity-oriented analog placement with diffusion sharing and well
               island generation},
  booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference,
               {ASP-DAC} 2010, Taipei, Taiwan, January 18-21, 2010},
  pages     = {305--311},
  year      = {2010},
  crossref  = {DBLP:conf/aspdac/2010},
  url       = {https://doi.org/10.1109/ASPDAC.2010.5419878},
  doi       = {10.1109/ASPDAC.2010.5419878},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/aspdac/NakatakeKIKKIH10},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LiuFYN10,
  author    = {Bo Liu and
               Toru Fujimura and
               Bo Yang and
               Shigetoshi Nakatake},
  title     = {{D-A} converter based variation analysis for analog layout design},
  booktitle = {Proceedings of the 15th Asia South Pacific Design Automation Conference,
               {ASP-DAC} 2010, Taipei, Taiwan, January 18-21, 2010},
  pages     = {843--848},
  year      = {2010},
  crossref  = {DBLP:conf/aspdac/2010},
  url       = {https://doi.org/10.1109/ASPDAC.2010.5419687},
  doi       = {10.1109/ASPDAC.2010.5419687},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/aspdac/LiuFYN10},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/YangDLN10,
  author    = {Bo Yang and
               Qing Dong and
               Jing Li and
               Shigetoshi Nakatake},
  title     = {Structured analog circuit design and {MOS} transistor decomposition
               for high accuracy applications},
  booktitle = {2010 International Conference on Computer-Aided Design, {ICCAD} 2010,
               San Jose, CA, USA, November 7-11, 2010},
  pages     = {721--728},
  year      = {2010},
  crossref  = {DBLP:conf/iccad/2010},
  url       = {https://doi.org/10.1109/ICCAD.2010.5654264},
  doi       = {10.1109/ICCAD.2010.5654264},
  timestamp = {Mon, 11 Feb 2019 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/iccad/YangDLN10},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LiYDN10,
  author    = {Jing Li and
               Bo Yang and
               Qing Dong and
               Shigetoshi Nakatake},
  title     = {Post-placement {STI} well width adjusting by geometric programming
               for device mobility enhancement in critical path},
  booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2010), May
               30 - June 2, 2010, Paris, France},
  pages     = {929--932},
  year      = {2010},
  crossref  = {DBLP:conf/iscas/2010},
  url       = {https://doi.org/10.1109/ISCAS.2010.5537398},
  doi       = {10.1109/ISCAS.2010.5537398},
  timestamp = {Tue, 22 May 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iscas/LiYDN10},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/YangN09,
  author    = {Bo Yang and
               Shigetoshi Nakatake},
  title     = {Fast Shape Optimization of Metalization Patterns for Power-MOSFET
               Based Driver},
  journal   = {{IEICE} Transactions},
  volume    = {92-A},
  number    = {12},
  pages     = {3052--3060},
  year      = {2009},
  url       = {https://doi.org/10.1587/transfun.E92.A.3052},
  doi       = {10.1587/transfun.E92.A.3052},
  timestamp = {Sat, 29 Sep 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/ieicet/YangN09},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/DongYLN09,
  author    = {Qing Dong and
               Bo Yang and
               Jing Li and
               Shigetoshi Nakatake},
  title     = {Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric
               Programming},
  journal   = {{IEICE} Transactions},
  volume    = {92-A},
  number    = {12},
  pages     = {3103--3110},
  year      = {2009},
  url       = {https://doi.org/10.1587/transfun.E92.A.3103},
  doi       = {10.1587/transfun.E92.A.3103},
  timestamp = {Sat, 29 Sep 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/ieicet/DongYLN09},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/DongN09,
  author    = {Qing Dong and
               Shigetoshi Nakatake},
  title     = {Structured Placement with Topological Regularity Evaluation},
  journal   = {{IPSJ} Trans. System {LSI} Design Methodology},
  volume    = {2},
  pages     = {222--238},
  year      = {2009},
  url       = {https://doi.org/10.2197/ipsjtsldm.2.222},
  doi       = {10.2197/ipsjtsldm.2.222},
  timestamp = {Tue, 22 May 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/ipsj/DongN09},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/LiYHDN09,
  author    = {Jing Li and
               Bo Yang and
               Xiaochuan Hu and
               Qing Dong and
               Shigetoshi Nakatake},
  title     = {{STI} stress aware placement optimization based on geometric programming},
  booktitle = {Proceedings of the 19th {ACM} Great Lakes Symposium on {VLSI} 2009,
               Boston Area, MA, USA, May 10-12 2009},
  pages     = {209--214},
  year      = {2009},
  crossref  = {DBLP:conf/glvlsi/2009},
  url       = {https://doi.org/10.1145/1531542.1531594},
  doi       = {10.1145/1531542.1531594},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/glvlsi/LiYHDN09},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/DongYLN09,
  author    = {Qing Dong and
               Bo Yang and
               Jing Li and
               Shigetoshi Nakatake},
  title     = {Incremental buffer insertion and module resizing algorithm using geometric
               programming},
  booktitle = {Proceedings of the 19th {ACM} Great Lakes Symposium on {VLSI} 2009,
               Boston Area, MA, USA, May 10-12 2009},
  pages     = {413--416},
  year      = {2009},
  crossref  = {DBLP:conf/glvlsi/2009},
  url       = {https://doi.org/10.1145/1531542.1531636},
  doi       = {10.1145/1531542.1531636},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/glvlsi/DongYLN09},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/YangMN08,
  author    = {Bo Yang and
               Hiroshi Murata and
               Shigetoshi Nakatake},
  title     = {A Finite Element-Domain Decomposition Coupled Resistance Extraction
               Method with Virtual Terminal Insertion},
  journal   = {{IEICE} Transactions},
  volume    = {91-A},
  number    = {2},
  pages     = {542--549},
  year      = {2008},
  url       = {https://doi.org/10.1093/ietfec/e91-a.2.542},
  doi       = {10.1093/ietfec/e91-a.2.542},
  timestamp = {Sun, 28 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/ieicet/YangMN08},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/DongN08,
  author    = {Qing Dong and
               Shigetoshi Nakatake},
  title     = {Constraint-free analog placement with topological symmetry structure},
  booktitle = {Proceedings of the 13th Asia South Pacific Design Automation Conference,
               {ASP-DAC} 2008, Seoul, Korea, January 21-24, 2008},
  pages     = {186--191},
  year      = {2008},
  crossref  = {DBLP:conf/aspdac/2008},
  url       = {https://doi.org/10.1109/ASPDAC.2008.4483937},
  doi       = {10.1109/ASPDAC.2008.4483937},
  timestamp = {Tue, 22 May 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/aspdac/DongN08},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/FujimuraN08,
  author    = {Toru Fujimura and
               Shigetoshi Nakatake},
  title     = {Transistor-level programmable {MOS} analog {IC} with body biasing},
  booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2008), 18-21
               May 2008, Sheraton Seattle Hotel, Seattle, Washington, {USA}},
  pages     = {153--156},
  year      = {2008},
  crossref  = {DBLP:conf/iscas/2008},
  url       = {https://doi.org/10.1109/ISCAS.2008.4541377},
  doi       = {10.1109/ISCAS.2008.4541377},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iscas/FujimuraN08},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/YangNM08,
  author    = {Bo Yang and
               Shigetoshi Nakatake and
               Hiroshi Murata},
  title     = {Fast Shape Optimization of Metallization Patterns for {DMOS} Based
               Driver},
  booktitle = {9th International Symposium on Quality of Electronic Design {(ISQED}
               2008), 17-19 March 2008, San Jose, CA, {USA}},
  pages     = {617--620},
  year      = {2008},
  crossref  = {DBLP:conf/isqed/2008},
  url       = {https://doi.org/10.1109/ISQED.2008.4479808},
  doi       = {10.1109/ISQED.2008.4479808},
  timestamp = {Thu, 11 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isqed/YangNM08},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/Nakatake07,
  author    = {Shigetoshi Nakatake},
  title     = {Structured Placement with Topological Regularity Evaluation},
  booktitle = {Proceedings of the 12th Conference on Asia South Pacific Design Automation,
               {ASP-DAC} 2007, Yokohama, Japan, January 23-26, 2007},
  pages     = {215--220},
  year      = {2007},
  crossref  = {DBLP:conf/aspdac/2007},
  url       = {https://doi.org/10.1109/ASPDAC.2007.357988},
  doi       = {10.1109/ASPDAC.2007.357988},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/aspdac/Nakatake07},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/NakatakeKTS07,
  author    = {Shigetoshi Nakatake and
               Zohreh Karimi and
               Taraneh Taghavi and
               Majid Sarrafzadeh},
  title     = {Block placement to ensure channel routability},
  booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
               Stresa, Lago Maggiore, Italy, March 11-13, 2007},
  pages     = {465--468},
  year      = {2007},
  crossref  = {DBLP:conf/glvlsi/2007},
  url       = {https://doi.org/10.1145/1228784.1228894},
  doi       = {10.1145/1228784.1228894},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/glvlsi/NakatakeKTS07},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/FuNTK06,
  author    = {Ning Fu and
               Shigetoshi Nakatake and
               Yasuhiro Takashima and
               Yoji Kajitani},
  title     = {The Oct-Touched Tile: {A} New Architecture for Shape-Based Routing},
  journal   = {{IEICE} Transactions},
  volume    = {89-A},
  number    = {2},
  pages     = {448--455},
  year      = {2006},
  url       = {https://doi.org/10.1093/ietfec/e89-a.2.448},
  doi       = {10.1093/ietfec/e89-a.2.448},
  timestamp = {Sun, 28 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/ieicet/FuNTK06},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/NojimaONFOK06,
  author    = {Takashi Nojima and
               Nobuto Ono and
               Shigetoshi Nakatake and
               Toru Fujimura and
               Koji Okazaki and
               Yoji Kajitani},
  title     = {Adaptive Porting of Analog IPs with Reusable Conservative Properties},
  booktitle = {2006 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
               2006), 2-3 March 2006, Karlsruhe, Germany},
  pages     = {18--23},
  year      = {2006},
  crossref  = {DBLP:conf/isvlsi/2006},
  url       = {https://doi.org/10.1109/ISVLSI.2006.15},
  doi       = {10.1109/ISVLSI.2006.15},
  timestamp = {Sun, 21 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isvlsi/NojimaONFOK06},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/FuMN06,
  author    = {Ning Fu and
               Mitsutoshi Mineshima and
               Shigetoshi Nakatake},
  title     = {Multi-SP: {A} Representation with United Rectangles for Analog Placement
               and Routing},
  booktitle = {2006 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
               2006), 2-3 March 2006, Karlsruhe, Germany},
  pages     = {38--43},
  year      = {2006},
  crossref  = {DBLP:conf/isvlsi/2006},
  url       = {https://doi.org/10.1109/ISVLSI.2006.64},
  doi       = {10.1109/ISVLSI.2006.64},
  timestamp = {Sun, 21 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isvlsi/FuMN06},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/YanNN06,
  author    = {Tan Yan and
               Shigetoshi Nakatake and
               Takashi Nojima},
  title     = {Formulating the Empirical Strategies in Module Generation of Analog
               {MOS} Layout},
  booktitle = {2006 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
               2006), 2-3 March 2006, Karlsruhe, Germany},
  pages     = {44--49},
  year      = {2006},
  crossref  = {DBLP:conf/isvlsi/2006},
  url       = {https://doi.org/10.1109/ISVLSI.2006.47},
  doi       = {10.1109/ISVLSI.2006.47},
  timestamp = {Sun, 21 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isvlsi/YanNN06},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/FuNTK05,
  author    = {Ning Fu and
               Shigetoshi Nakatake and
               Yasuhiro Takashima and
               Yoji Kajitani},
  title     = {The oct-touched tile: a new architecture for shape-based routing},
  booktitle = {Proceedings of the 15th {ACM} Great Lakes Symposium on {VLSI} 2005,
               Chicago, Illinois, USA, April 17-19, 2005},
  pages     = {126--129},
  year      = {2005},
  crossref  = {DBLP:conf/glvlsi/2005},
  url       = {https://doi.org/10.1145/1057661.1057692},
  doi       = {10.1145/1057661.1057692},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/glvlsi/FuNTK05},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/FuNTK04,
  author    = {Ning Fu and
               Shigetoshi Nakatake and
               Yasuhiro Takashima and
               Yoji Kajitani},
  title     = {Abstraction and optimization of consistent floorplanning with pillar
               block constraints},
  booktitle = {Proceedings of the 2004 Conference on Asia South Pacific Design Automation:
               Electronic Design and Solution Fair 2004, Yokohama, Japan, January
               27-30, 2004},
  pages     = {19--24},
  year      = {2004},
  crossref  = {DBLP:conf/aspdac/2004},
  url       = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2004.38},
  doi       = {10.1109/ASPDAC.2004.38},
  timestamp = {Tue, 27 Nov 2018 15:52:28 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/aspdac/FuNTK04},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/NojimaZTNK04,
  author    = {Takashi Nojima and
               Xiaoke Zhu and
               Yasuhiro Takashima and
               Shigetoshi Nakatake and
               Yoji Kajitani},
  title     = {Multi-level placement with circuit schema based clustering in analog
               {IC} layouts},
  booktitle = {Proceedings of the 2004 Conference on Asia South Pacific Design Automation:
               Electronic Design and Solution Fair 2004, Yokohama, Japan, January
               27-30, 2004},
  pages     = {406--411},
  year      = {2004},
  crossref  = {DBLP:conf/aspdac/2004},
  url       = {http://doi.ieeecomputersociety.org/10.1109/ASPDAC.2004.142},
  doi       = {10.1109/ASPDAC.2004.142},
  timestamp = {Tue, 27 Nov 2018 15:52:28 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/aspdac/NojimaZTNK04},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/NojimaTNK04,
  author    = {Takashi Nojima and
               Yasuhiro Takashima and
               Shigetoshi Nakatake and
               Yoji Kajitani},
  title     = {A device-level placement with multi-directional convex clustering},
  booktitle = {Proceedings of the 14th {ACM} Great Lakes Symposium on {VLSI} 2004,
               Boston, MA, USA, April 26-28, 2004},
  pages     = {196--201},
  year      = {2004},
  crossref  = {DBLP:conf/glvlsi/2004},
  url       = {https://doi.org/10.1145/988952.989001},
  doi       = {10.1145/988952.989001},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/glvlsi/NojimaTNK04},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KidaZZTN04,
  author    = {Keiji Kida and
               Xiaoke Zhu and
               Changwen Zhuang and
               Yasuhiro Takashima and
               Shigetoshi Nakatake},
  title     = {A fast algorithm for crosspoint assignment under crosstalk constraints
               with shielding effects},
  booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
               {ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
  pages     = {489--492},
  year      = {2004},
  crossref  = {DBLP:conf/iscas/2004},
  timestamp = {Fri, 20 May 2016 09:53:46 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iscas/KidaZZTN04},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NakatakeKK02,
  author    = {Shigetoshi Nakatake and
               Yukiko Kubo and
               Yoji Kajitani},
  title     = {Consistent floorplanning with hierarchical superconstraints},
  journal   = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems},
  volume    = {21},
  number    = {1},
  pages     = {42--49},
  year      = {2002},
  url       = {https://doi.org/10.1109/43.974136},
  doi       = {10.1109/43.974136},
  timestamp = {Sat, 20 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/tcad/NakatakeKK02},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/KuboNKK02,
  author    = {Yukiko Kubo and
               Shigetoshi Nakatake and
               Yoji Kajitani and
               Masahiro Kawakita},
  title     = {Chip size estimation based on wiring area},
  booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems 2002, {APCCAS}
               2002, Singapore, 16-18 December 2002},
  pages     = {113--118},
  year      = {2002},
  crossref  = {DBLP:conf/apccas/2002},
  url       = {https://doi.org/10.1109/APCCAS.2002.1115136},
  doi       = {10.1109/APCCAS.2002.1115136},
  timestamp = {Wed, 17 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/apccas/KuboNKK02},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/KuboNKK02,
  author    = {Yukiko Kubo and
               Shigetoshi Nakatake and
               Yoji Kajitani and
               Masahiro Kawakita},
  title     = {Explicit Expression and Simultaneous Optimization of Placement and
               Routing for Analog {IC} Layouts},
  booktitle = {Proceedings of the {ASPDAC} 2002 / {VLSI} Design 2002, CD-ROM, 7-11
               January 2002, Bangalore, India},
  pages     = {467--472},
  year      = {2002},
  crossref  = {DBLP:conf/vlsid/2002},
  url       = {https://doi.org/10.1109/ASPDAC.2002.994964},
  doi       = {10.1109/ASPDAC.2002.994964},
  timestamp = {Tue, 23 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/vlsid/KuboNKK02},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ispd/NakatakeKK01,
  author    = {Shigetoshi Nakatake and
               Yukiko Kubo and
               Yoji Kajitani},
  title     = {Consistent floorplanning with super hierarchical constraints},
  booktitle = {Proceedings of the 2001 International Symposium on Physical Design,
               {ISPD} 2001, Sonoma County, CA, USA, April 1-4, 2001},
  pages     = {144--149},
  year      = {2001},
  crossref  = {DBLP:conf/ispd/2001},
  url       = {https://doi.org/10.1145/369691.369755},
  doi       = {10.1145/369691.369755},
  timestamp = {Tue, 06 Nov 2018 11:07:47 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/ispd/NakatakeKK01},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KuboTNK00,
  author    = {Yukiko Kubo and
               Yasuhiro Takashima and
               Shigetoshi Nakatake and
               Yoji Kajitani},
  title     = {Self-reforming routing for stochastic search in {VLSI} interconnection
               layout},
  booktitle = {Proceedings of {ASP-DAC} 2000, Asia and South Pacific Design Automation
               Conference 2000, Yokohama, Japan},
  pages     = {87--92},
  year      = {2000},
  crossref  = {DBLP:conf/aspdac/2000},
  url       = {https://doi.org/10.1145/368434.368584},
  doi       = {10.1145/368434.368584},
  timestamp = {Tue, 06 Nov 2018 16:57:18 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/aspdac/KuboTNK00},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/KajitaniTAN00,
  author    = {Yoji Kajitani and
               Atsushi Takahashi and
               Kengo R. Azegami and
               Shigetoshi Nakatake},
  title     = {Partition, Packing and Clock Distribution-A New Paradigm of Physical
               Design},
  booktitle = {13th International Conference on {VLSI} Design {(VLSI} Design 2000),
               4-7 January 2000, Calcutta, India},
  pages     = {11},
  year      = {2000},
  crossref  = {DBLP:conf/vlsid/2000},
  url       = {https://doi.org/10.1109/ICVD.2000.812577},
  doi       = {10.1109/ICVD.2000.812577},
  timestamp = {Tue, 23 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/vlsid/KajitaniTAN00},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NakatakeFMK98,
  author    = {Shigetoshi Nakatake and
               Kunihiro Fujiyoshi and
               Hiroshi Murata and
               Yoji Kajitani},
  title     = {Module packing based on the BSG-structure and {IC} layout applications},
  journal   = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems},
  volume    = {17},
  number    = {6},
  pages     = {519--530},
  year      = {1998},
  url       = {https://doi.org/10.1109/43.703832},
  doi       = {10.1109/43.703832},
  timestamp = {Sat, 20 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/tcad/NakatakeFMK98},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/NakatakeFK98,
  author    = {Shigetoshi Nakatake and
               Masahiro Furuya and
               Yoji Kajitani},
  title     = {Module Placement on BSG-Structure with Pre-Placed Modules and Rectilinear
               Modules},
  booktitle = {Proceedings of the {ASP-DAC} '98, Asia and South Pacific Design Automation
               Conference 1998, Pacifico Yokohama, Yokohama, Japan, February 10-13,
               1998},
  pages     = {571--576},
  year      = {1998},
  crossref  = {DBLP:conf/aspdac/1998},
  url       = {https://doi.org/10.1109/ASPDAC.1998.669558},
  doi       = {10.1109/ASPDAC.1998.669558},
  timestamp = {Fri, 26 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/aspdac/NakatakeFK98},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/SakanushiNK98,
  author    = {Keishi Sakanushi and
               Shigetoshi Nakatake and
               Yoji Kajitani},
  title     = {The multi-BSG: stochastic approach to an optimum packing of convex-rectilinear
               blocks},
  booktitle = {Proceedings of the 1998 {IEEE/ACM} International Conference on Computer-Aided
               Design, {ICCAD} 1998, San Jose, CA, USA, November 8-12, 1998},
  pages     = {267--274},
  year      = {1998},
  crossref  = {DBLP:conf/iccad/1998},
  url       = {https://doi.org/10.1145/288548.288624},
  doi       = {10.1145/288548.288624},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/iccad/SakanushiNK98},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/NakatakeSKK98,
  author    = {Shigetoshi Nakatake and
               Keishi Sakanushi and
               Yoji Kajitani and
               Masahiro Kawakita},
  title     = {The channeled-BSG: a universal floorplan for simultaneous place/route
               with {IC} applications},
  booktitle = {Proceedings of the 1998 {IEEE/ACM} International Conference on Computer-Aided
               Design, {ICCAD} 1998, San Jose, CA, USA, November 8-12, 1998},
  pages     = {418--425},
  year      = {1998},
  crossref  = {DBLP:conf/iccad/1998},
  url       = {https://doi.org/10.1145/288548.289064},
  doi       = {10.1145/288548.289064},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/iccad/NakatakeSKK98},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MurataFNK96,
  author    = {Hiroshi Murata and
               Kunihiro Fujiyoshi and
               Shigetoshi Nakatake and
               Yoji Kajitani},
  title     = {{VLSI} module placement based on rectangle-packing by the sequence-pair},
  journal   = {{IEEE} Trans. on {CAD} of Integrated Circuits and Systems},
  volume    = {15},
  number    = {12},
  pages     = {1518--1524},
  year      = {1996},
  url       = {https://doi.org/10.1109/43.552084},
  doi       = {10.1109/43.552084},
  timestamp = {Sat, 20 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/tcad/MurataFNK96},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/NakatakeFMK96,
  author    = {Shigetoshi Nakatake and
               Kunihiro Fujiyoshi and
               Hiroshi Murata and
               Yoji Kajitani},
  title     = {Module placement on BSG-structure and {IC} layout applications},
  booktitle = {{ICCAD}},
  pages     = {484--491},
  year      = {1996},
  url       = {https://doi.org/10.1109/ICCAD.1996.569870},
  doi       = {10.1109/ICCAD.1996.569870},
  timestamp = {Mon, 26 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/iccad/NakatakeFMK96},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/MurataFNK95,
  author    = {Hiroshi Murata and
               Kunihiro Fujiyoshi and
               Shigetoshi Nakatake and
               Yoji Kajitani},
  title     = {Rectangle-packing-based module placement},
  booktitle = {Proceedings of the 1995 {IEEE/ACM} International Conference on Computer-Aided
               Design, {ICCAD} 1995, San Jose, California, USA, November 5-9, 1995},
  pages     = {472--479},
  year      = {1995},
  crossref  = {DBLP:conf/iccad/1995},
  url       = {https://doi.org/10.1109/ICCAD.1995.480159},
  doi       = {10.1109/ICCAD.1995.480159},
  timestamp = {Mon, 26 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/iccad/MurataFNK95},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/NakatakeK94,
  author    = {Shigetoshi Nakatake and
               Yoji Kajitani},
  title     = {Channel-driven global routing with consistent placement (extended
               abstract)},
  booktitle = {Proceedings of the 1994 {IEEE/ACM} International Conference on Computer-Aided
               Design, {ICCAD} 1994, San Jose, California, USA, November 6-10, 1994},
  pages     = {350--355},
  year      = {1994},
  crossref  = {DBLP:conf/iccad/1994},
  url       = {https://doi.org/10.1109/ICCAD.1994.629816},
  doi       = {10.1109/ICCAD.1994.629816},
  timestamp = {Mon, 11 Feb 2019 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/iccad/NakatakeK94},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/mwscas/2018,
  title     = {{IEEE} 61st International Midwest Symposium on Circuits and Systems,
               {MWSCAS} 2018, Windsor, ON, Canada, August 5-8, 2018},
  publisher = {{IEEE}},
  year      = {2018},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8610060},
  isbn      = {978-1-5386-7392-8},
  timestamp = {Wed, 17 Apr 2019 09:51:21 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/mwscas/2018},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/ngcas/2018,
  title     = {2018 New Generation of CAS, {NGCAS} 2018, Valletta, Malta, November
               20-23, 2018},
  publisher = {{IEEE}},
  year      = {2018},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8554190},
  isbn      = {978-1-5386-7681-3},
  timestamp = {Thu, 20 Dec 2018 09:01:24 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/ngcas/2018},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/glvlsi/2017,
  editor    = {Laleh Behjat and
               Jie Han and
               Miroslav N. Velev and
               Deming Chen},
  title     = {Proceedings of the on Great Lakes Symposium on {VLSI} 2017, Banff,
               AB, Canada, May 10-12, 2017},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3060403},
  doi       = {10.1145/3060403},
  isbn      = {978-1-4503-4972-7},
  timestamp = {Tue, 06 Nov 2018 16:59:34 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/glvlsi/2017},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/iccad/2017,
  editor    = {Sri Parameswaran},
  title     = {2017 {IEEE/ACM} International Conference on Computer-Aided Design,
               {ICCAD} 2017, Irvine, CA, USA, November 13-16, 2017},
  publisher = {{IEEE}},
  year      = {2017},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8167715},
  isbn      = {978-1-5386-3093-8},
  timestamp = {Mon, 09 Apr 2018 15:38:24 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iccad/2017},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/ngcas/2017,
  title     = {New Generation of CAS, {NGCAS} 2017, Genova, Italy, September 6-9,
               2017},
  publisher = {{IEEE}},
  year      = {2017},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8049744},
  isbn      = {978-1-5090-6447-2},
  timestamp = {Fri, 27 Oct 2017 14:04:25 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/ngcas/2017},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/iccad/2016,
  editor    = {Frank Liu},
  title     = {Proceedings of the 35th International Conference on Computer-Aided
               Design, {ICCAD} 2016, Austin, TX, USA, November 7-10, 2016},
  publisher = {{ACM}},
  year      = {2016},
  url       = {https://doi.org/10.1145/2966986},
  doi       = {10.1145/2966986},
  isbn      = {978-1-4503-4466-1},
  timestamp = {Tue, 06 Nov 2018 11:07:08 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/iccad/2016},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/icecsys/2016,
  title     = {2016 {IEEE} International Conference on Electronics, Circuits and
               Systems, {ICECS} 2016, Monte Carlo, Monaco, December 11-14, 2016},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7829200},
  isbn      = {978-1-5090-6113-6},
  timestamp = {Fri, 10 Feb 2017 17:32:04 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/icecsys/2016},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/reconfig/2016,
  editor    = {Peter M. Athanas and
               Ren{\'{e}} Cumplido and
               Claudia Feregrino and
               Ron Sass},
  title     = {International Conference on ReConFigurable Computing and FPGAs, ReConFig
               2016, Cancun, Mexico, November 30 - Dec. 2, 2016},
  publisher = {{IEEE}},
  year      = {2016},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7838017},
  isbn      = {978-1-5090-3707-0},
  timestamp = {Mon, 20 Feb 2017 11:34:08 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/reconfig/2016},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/iscas/2015,
  title     = {2015 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
               2015, Lisbon, Portugal, May 24-27, 2015},
  publisher = {{IEEE}},
  year      = {2015},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7152138},
  isbn      = {978-1-4799-8391-9},
  timestamp = {Wed, 05 Aug 2015 09:08:53 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iscas/2015},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isvlsi/2015,
  title     = {2015 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2015,
               Montpellier, France, July 8-10, 2015},
  publisher = {{IEEE} Computer Society},
  year      = {2015},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7307713},
  isbn      = {978-1-4799-8719-1},
  timestamp = {Fri, 06 May 2016 09:24:18 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isvlsi/2015},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/glvlsi/2013,
  editor    = {Jos{\'{e}} Luis Ayala and
               Alex K. Jones and
               Patrick H. Madden and
               Ayse Kivilcim Coskun},
  title     = {Great Lakes Symposium on {VLSI} 2013 (part of ECRC), GLSVLSI'13, Paris,
               France, May 2-4, 2013},
  publisher = {{ACM}},
  year      = {2013},
  url       = {https://doi.org/10.1145/2483028},
  doi       = {10.1145/2483028},
  isbn      = {978-1-4503-2032-0},
  timestamp = {Wed, 24 May 2017 08:28:02 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/glvlsi/2013},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/ispd/2013,
  editor    = {Cheng{-}Kok Koh and
               Cliff C. N. Sze},
  title     = {International Symposium on Physical Design, ISPD'13, Stateline, NV,
               USA, March 24-27, 2013},
  publisher = {{ACM}},
  year      = {2013},
  url       = {https://doi.org/10.1145/2451916},
  doi       = {10.1145/2451916},
  isbn      = {978-1-4503-1954-6},
  timestamp = {Tue, 06 Nov 2018 11:07:47 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/ispd/2013},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isqed/2013,
  title     = {International Symposium on Quality Electronic Design, {ISQED} 2013,
               Santa Clara, CA, USA, March 4-6, 2013},
  publisher = {{IEEE}},
  year      = {2013},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6520923},
  isbn      = {978-1-4673-4951-2},
  timestamp = {Mon, 10 Jun 2013 19:39:41 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isqed/2013},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2013soc,
  editor    = {Martin Margala and
               Ricardo Augusto da Luz Reis and
               Alex Orailoglu and
               Luigi Carro and
               Lu{\'{\i}}s Miguel Silveira and
               H. Fatih Ugurdag},
  title     = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
               VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
  publisher = {{IEEE}},
  year      = {2013},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6662534},
  isbn      = {978-1-4799-0522-5},
  timestamp = {Thu, 11 May 2017 16:22:21 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/vlsi/2013soc},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/iscas/2012,
  title     = {2012 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
               2012, Seoul, Korea (South), May 20-23, 2012},
  publisher = {{IEEE}},
  year      = {2012},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6257548},
  isbn      = {978-1-4673-0218-0},
  timestamp = {Mon, 08 Oct 2012 14:49:04 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iscas/2012},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isqed/2012,
  editor    = {Keith A. Bowman and
               Kamesh V. Gadepally and
               Pallab Chatterjee and
               Mark M. Budnik and
               Lalitha Immaneni},
  title     = {Thirteenth International Symposium on Quality Electronic Design, {ISQED}
               2012, Santa Clara, CA, USA, March 19-21, 2012},
  publisher = {{IEEE}},
  year      = {2012},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6182938},
  isbn      = {978-1-4673-1034-5},
  timestamp = {Thu, 26 Apr 2012 15:39:37 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isqed/2012},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/glvlsi/2011,
  editor    = {David Atienza and
               Yuan Xie and
               Jos{\'{e}} L. Ayala and
               Ken S. Stevens},
  title     = {Proceedings of the 21st {ACM} Great Lakes Symposium on {VLSI} 2010,
               Lausanne, Switzerland, May 2-6, 2011},
  publisher = {{ACM}},
  year      = {2011},
  url       = {https://doi.org/10.1145/1973009},
  doi       = {10.1145/1973009},
  isbn      = {978-1-4503-0667-6},
  timestamp = {Wed, 24 May 2017 08:28:02 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/glvlsi/2011},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isqed/2011,
  title     = {Proceedings of the 12th International Symposium on Quality Electronic
               Design, {ISQED} 2011, Santa Clara, California, USA, 14-16 March 2011},
  publisher = {{IEEE}},
  year      = {2011},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5764309},
  isbn      = {978-1-61284-914-0},
  timestamp = {Fri, 26 Sep 2014 14:08:24 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isqed/2011},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/aspdac/2010,
  title     = {Proceedings of the 15th Asia South Pacific Design Automation Conference,
               {ASP-DAC} 2010, Taipei, Taiwan, January 18-21, 2010},
  publisher = {{IEEE}},
  year      = {2010},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5415928},
  isbn      = {978-1-60558-837-7},
  timestamp = {Fri, 20 May 2016 11:34:47 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/aspdac/2010},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/iccad/2010,
  editor    = {Louis Scheffer and
               Joel R. Phillips and
               Alan J. Hu},
  title     = {2010 International Conference on Computer-Aided Design, {ICCAD} 2010,
               San Jose, CA, USA, November 7-11, 2010},
  publisher = {{IEEE}},
  year      = {2010},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5638200},
  isbn      = {978-1-4244-8192-7},
  timestamp = {Thu, 30 Apr 2015 18:34:30 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iccad/2010},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/iscas/2010,
  title     = {International Symposium on Circuits and Systems {(ISCAS} 2010), May
               30 - June 2, 2010, Paris, France},
  publisher = {{IEEE}},
  year      = {2010},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5512009},
  isbn      = {978-1-4244-5308-5},
  timestamp = {Fri, 20 May 2016 09:38:10 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iscas/2010},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/glvlsi/2009,
  editor    = {Fabrizio Lombardi and
               Sanjukta Bhanja and
               Yehia Massoud and
               R. Iris Bahar},
  title     = {Proceedings of the 19th {ACM} Great Lakes Symposium on {VLSI} 2009,
               Boston Area, MA, USA, May 10-12 2009},
  publisher = {{ACM}},
  year      = {2009},
  url       = {https://doi.org/10.1145/1531542},
  doi       = {10.1145/1531542},
  isbn      = {978-1-60558-522-2},
  timestamp = {Wed, 24 May 2017 08:28:02 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/glvlsi/2009},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/aspdac/2008,
  editor    = {Chong{-}Min Kyung and
               Kiyoung Choi and
               Soonhoi Ha},
  title     = {Proceedings of the 13th Asia South Pacific Design Automation Conference,
               {ASP-DAC} 2008, Seoul, Korea, January 21-24, 2008},
  publisher = {{IEEE}},
  year      = {2008},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=4480121},
  isbn      = {978-1-4244-1921-0},
  timestamp = {Fri, 20 May 2016 11:45:51 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/aspdac/2008},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/iscas/2008,
  title     = {International Symposium on Circuits and Systems {(ISCAS} 2008), 18-21
               May 2008, Sheraton Seattle Hotel, Seattle, Washington, {USA}},
  publisher = {{IEEE}},
  year      = {2008},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=4534149},
  isbn      = {978-1-4244-1683-7},
  timestamp = {Fri, 20 May 2016 09:40:26 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iscas/2008},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isqed/2008,
  title     = {9th International Symposium on Quality of Electronic Design {(ISQED}
               2008), 17-19 March 2008, San Jose, CA, {USA}},
  publisher = {{IEEE} Computer Society},
  year      = {2008},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=4479672},
  isbn      = {978-0-7695-3117-5},
  timestamp = {Fri, 26 Sep 2014 14:08:24 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isqed/2008},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/aspdac/2007,
  title     = {Proceedings of the 12th Conference on Asia South Pacific Design Automation,
               {ASP-DAC} 2007, Yokohama, Japan, January 23-26, 2007},
  publisher = {{IEEE} Computer Society},
  year      = {2007},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=4195969},
  isbn      = {1-4244-0629-3},
  timestamp = {Fri, 20 May 2016 11:21:59 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/aspdac/2007},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/glvlsi/2007,
  editor    = {Hai Zhou and
               Enrico Macii and
               Zhiyuan Yan and
               Yehia Massoud},
  title     = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
               Stresa, Lago Maggiore, Italy, March 11-13, 2007},
  publisher = {{ACM}},
  year      = {2007},
  url       = {https://doi.org/10.1145/1228784},
  doi       = {10.1145/1228784},
  isbn      = {978-1-59593-605-9},
  timestamp = {Wed, 24 May 2017 08:28:02 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/glvlsi/2007},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isvlsi/2006,
  title     = {2006 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
               2006), 2-3 March 2006, Karlsruhe, Germany},
  publisher = {{IEEE} Computer Society},
  year      = {2006},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=10672},
  isbn      = {0-7695-2533-4},
  timestamp = {Tue, 26 May 2015 18:40:57 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isvlsi/2006},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/glvlsi/2005,
  editor    = {John Lach and
               Gang Qu and
               Yehea I. Ismail},
  title     = {Proceedings of the 15th {ACM} Great Lakes Symposium on {VLSI} 2005,
               Chicago, Illinois, USA, April 17-19, 2005},
  publisher = {{ACM}},
  year      = {2005},
  url       = {https://doi.org/10.1145/1057661},
  doi       = {10.1145/1057661},
  isbn      = {1-59593-057-4},
  timestamp = {Wed, 24 May 2017 08:28:02 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/glvlsi/2005},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/aspdac/2004,
  editor    = {Masaharu Imai},
  title     = {Proceedings of the 2004 Conference on Asia South Pacific Design Automation:
               Electronic Design and Solution Fair 2004, Yokohama, Japan, January
               27-30, 2004},
  publisher = {{IEEE} Computer Society},
  year      = {2004},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9284},
  isbn      = {0-7803-8175-0},
  timestamp = {Tue, 27 Nov 2018 15:52:28 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/aspdac/2004},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/glvlsi/2004,
  editor    = {David Garrett and
               John Lach and
               Charles A. Zukowski},
  title     = {Proceedings of the 14th {ACM} Great Lakes Symposium on {VLSI} 2004,
               Boston, MA, USA, April 26-28, 2004},
  publisher = {{ACM}},
  year      = {2004},
  url       = {https://doi.org/10.1145/988952},
  doi       = {10.1145/988952},
  isbn      = {1-58113-853-9},
  timestamp = {Wed, 24 May 2017 08:28:02 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/glvlsi/2004},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/iscas/2004,
  title     = {Proceedings of the 2004 International Symposium on Circuits and Systems,
               {ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
  publisher = {{IEEE}},
  year      = {2004},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=9255},
  isbn      = {0-7803-8251-X},
  timestamp = {Fri, 20 May 2016 09:53:46 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iscas/2004},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/apccas/2002,
  title     = {{IEEE} Asia Pacific Conference on Circuits and Systems 2002, {APCCAS}
               2002, Singapore, 16-18 December 2002},
  publisher = {{IEEE}},
  year      = {2002},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=8182},
  isbn      = {0-7803-7690-0},
  timestamp = {Fri, 08 May 2015 15:30:14 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/apccas/2002},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsid/2002,
  title     = {Proceedings of the {ASPDAC} 2002 / {VLSI} Design 2002, CD-ROM, 7-11
               January 2002, Bangalore, India},
  publisher = {{IEEE} Computer Society},
  year      = {2002},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7806},
  isbn      = {0-7695-1299-2},
  timestamp = {Tue, 10 Nov 2015 10:39:02 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/vlsid/2002},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/ispd/2001,
  editor    = {Sachin S. Sapatnekar and
               Manfred Wiesel},
  title     = {Proceedings of the 2001 International Symposium on Physical Design,
               {ISPD} 2001, Sonoma County, CA, USA, April 1-4, 2001},
  publisher = {{ACM}},
  year      = {2001},
  url       = {https://doi.org/10.1145/369691},
  doi       = {10.1145/369691},
  isbn      = {1-58113-347-2},
  timestamp = {Tue, 06 Nov 2018 11:07:47 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/ispd/2001},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/aspdac/2000,
  title     = {Proceedings of {ASP-DAC} 2000, Asia and South Pacific Design Automation
               Conference 2000, Yokohama, Japan},
  publisher = {{ACM}},
  year      = {2000},
  url       = {https://doi.org/10.1145/368434},
  doi       = {10.1145/368434},
  isbn      = {0-7803-5974-7},
  timestamp = {Tue, 06 Nov 2018 16:57:18 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/aspdac/2000},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsid/2000,
  title     = {13th International Conference on {VLSI} Design {(VLSI} Design 2000),
               4-7 January 2000, Calcutta, India},
  publisher = {{IEEE} Computer Society},
  year      = {2000},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=6598},
  isbn      = {0-7695-0487-6},
  timestamp = {Mon, 20 Apr 2015 18:26:31 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/vlsid/2000},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/aspdac/1998,
  title     = {Proceedings of the {ASP-DAC} '98, Asia and South Pacific Design Automation
               Conference 1998, Pacifico Yokohama, Yokohama, Japan, February 10-13,
               1998},
  publisher = {{IEEE}},
  year      = {1998},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=5474},
  isbn      = {0-7803-4425-1},
  timestamp = {Tue, 30 Apr 2013 17:14:14 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/aspdac/1998},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/iccad/1998,
  editor    = {Hiroto Yasuura},
  title     = {Proceedings of the 1998 {IEEE/ACM} International Conference on Computer-Aided
               Design, {ICCAD} 1998, San Jose, CA, USA, November 8-12, 1998},
  publisher = {{ACM} / {IEEE} Computer Society},
  year      = {1998},
  url       = {http://dl.acm.org/citation.cfm?id=288548},
  isbn      = {1-58113-008-2},
  timestamp = {Thu, 30 Apr 2015 18:34:30 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iccad/1998},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/iccad/1995,
  editor    = {Richard L. Rudell},
  title     = {Proceedings of the 1995 {IEEE/ACM} International Conference on Computer-Aided
               Design, {ICCAD} 1995, San Jose, California, USA, November 5-9, 1995},
  publisher = {{IEEE} Computer Society / {ACM}},
  year      = {1995},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=3472},
  isbn      = {0-8186-7213-7},
  timestamp = {Thu, 30 Apr 2015 18:34:29 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iccad/1995},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/iccad/1994,
  editor    = {Jochen A. G. Jess and
               Richard L. Rudell},
  title     = {Proceedings of the 1994 {IEEE/ACM} International Conference on Computer-Aided
               Design, {ICCAD} 1994, San Jose, California, USA, November 6-10, 1994},
  publisher = {{IEEE} Computer Society / {ACM}},
  year      = {1994},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=4983},
  isbn      = {0-89791-690-5},
  timestamp = {Thu, 30 Apr 2015 18:34:27 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/iccad/1994},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
maintained by Schloss Dagstuhl LZI, founded at University of Trier