BibTeX records: Andrea Marchese

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@inproceedings{DBLP:conf/isvlsi/CremonaFMZZ17,
  author    = {Luca Cremona and
               William Fornaciari and
               Andrea Marchese and
               Michele Zanella and
               Davide Zoni},
  title     = {{DENA:} {A} DVFS-Capable Heterogeneous NoC Architecture},
  booktitle = {2017 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2017,
               Bochum, Germany, July 3-5, 2017},
  pages     = {489--494},
  year      = {2017},
  crossref  = {DBLP:conf/isvlsi/2017},
  url       = {https://doi.org/10.1109/ISVLSI.2017.91},
  doi       = {10.1109/ISVLSI.2017.91},
  timestamp = {Wed, 11 Apr 2018 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isvlsi/CremonaFMZZ17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hipeac/FornaciariPRMB16,
  author    = {William Fornaciari and
               Gianmario Pozzi and
               Federico Reghenzani and
               Andrea Marchese and
               Mauro Belluschi},
  title     = {Runtime resource management for embedded and {HPC} systems},
  booktitle = {Proceedings of the 7th Workshop on Parallel Programming and Run-Time
               Management Techniques for Many-core Architectures and the 5th Workshop
               on Design Tools and Architectures For Multicore Embedded Computing
               Platforms, {PARMA-DITAM} 2016, Prague, Czech Republic, January 18,
               2016},
  pages     = {31--36},
  year      = {2016},
  crossref  = {DBLP:conf/hipeac/2016parma},
  url       = {http://doi.acm.org/10.1145/2872421.2893173},
  doi       = {10.1145/2872421.2893173},
  timestamp = {Sat, 16 Sep 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/hipeac/FornaciariPRMB16},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/AntolaDM94,
  author    = {Anna Antola and
               Fausto Distante and
               Andrea Marchese},
  title     = {High level architectural synthesis: Precedence analysis and automatic
               cycle detection in data flow graphs},
  journal   = {Microprocessing and Microprogramming},
  volume    = {40},
  number    = {10-12},
  pages     = {693--696},
  year      = {1994},
  url       = {https://doi.org/10.1016/0165-6074(94)90020-5},
  doi       = {10.1016/0165-6074(94)90020-5},
  timestamp = {Sat, 20 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/jsa/AntolaDM94},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/AntolaDM93,
  author    = {Anna Antola and
               Fausto Distante and
               Andrea Marchese},
  title     = {High level synthesis through folding of data flow graphs: Optimal
               intra-node scheduling},
  journal   = {Microprocessing and Microprogramming},
  volume    = {39},
  number    = {2-5},
  pages     = {89--92},
  year      = {1993},
  url       = {https://doi.org/10.1016/0165-6074(93)90063-Q},
  doi       = {10.1016/0165-6074(93)90063-Q},
  timestamp = {Sat, 20 May 2017 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/bib/journals/jsa/AntolaDM93},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isvlsi/2017,
  title     = {2017 {IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2017,
               Bochum, Germany, July 3-5, 2017},
  publisher = {{IEEE}},
  year      = {2017},
  url       = {http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=7985547},
  isbn      = {978-1-5090-6762-6},
  timestamp = {Wed, 26 Jul 2017 18:00:27 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/isvlsi/2017},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/hipeac/2016parma,
  editor    = {Cristina Silvano and
               Jo{\~{a}}o M. P. Cardoso and
               Giovanni Agosta and
               Michael H{\"{u}}bner},
  title     = {Proceedings of the 7th Workshop on Parallel Programming and Run-Time
               Management Techniques for Many-core Architectures and the 5th Workshop
               on Design Tools and Architectures For Multicore Embedded Computing
               Platforms, {PARMA-DITAM} 2016, Prague, Czech Republic, January 18,
               2016},
  publisher = {{ACM}},
  year      = {2016},
  url       = {http://doi.acm.org/10.1145/2872421},
  doi       = {10.1145/2872421},
  isbn      = {978-1-4503-4052-6},
  timestamp = {Tue, 14 Jun 2016 08:50:05 +0200},
  biburl    = {https://dblp.org/rec/bib/conf/hipeac/2016parma},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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